Merge branch 'master' into efm32

examples/stm32/f1/Makefile.include

@@ -31,7 +31,8 @@ TOOLCHAIN_DIR   = ../../../../..
 CFLAGS		+= -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \
 		   -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F1
 LDSCRIPT	?= $(BINARY).ld
-LDFLAGS		+= -lc -lnosys -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f1 \
+LDFLAGS		+= -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \
+		   -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f1 \
 		   -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
 		   -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float
 OBJS		+= $(BINARY).o

examples/stm32/f2/Makefile.include

@@ -32,8 +32,8 @@ TOOLCHAIN_DIR   = ../../../../..
 CFLAGS		+= -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \
 		   -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F2
 LDSCRIPT	?= $(BINARY).ld
-LDFLAGS		+= -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \
+LDFLAGS		+= -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \
-			 -L$(TOOLCHAIN_DIR)/lib/stm32/f2 \
+		   -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f2 \
 		   -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
 		   -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float
 OBJS		+= $(BINARY).o

include/libopencm3/stm32/dac.h

@@ -0,0 +1,302 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+
+/* --- DAC registers ------------------------------------------------------- */
+
+/* DAC control register (DAC_CR) */
+#define DAC_CR				MMIO32(DAC_BASE + 0x00)
+
+/* DAC software trigger register (DAC_SWTRIGR) */
+#define DAC_SWTRIGR			MMIO32(DAC_BASE + 0x04)
+
+/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
+#define DAC_DHR12R1			MMIO32(DAC_BASE + 0x08)
+
+/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
+#define DAC_DHR12L1			MMIO32(DAC_BASE + 0x0C)
+
+/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
+#define DAC_DHR8R1			MMIO32(DAC_BASE + 0x10)
+
+/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
+#define DAC_DHR12R2			MMIO32(DAC_BASE + 0x14)
+
+/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
+#define DAC_DHR12L2			MMIO32(DAC_BASE + 0x18)
+
+/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
+#define DAC_DHR8R2			MMIO32(DAC_BASE + 0x1C)
+
+/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
+#define DAC_DHR12RD			MMIO32(DAC_BASE + 0x20)
+
+/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
+#define DAC_DHR12LD			MMIO32(DAC_BASE + 0x24)
+
+/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
+#define DAC_DHR8RD			MMIO32(DAC_BASE + 0x28)
+
+/* DAC channel1 data output register (DAC_DOR1) */
+#define DAC_DOR1			MMIO32(DAC_BASE + 0x2C)
+
+/* DAC channel2 data output register (DAC_DOR2) */
+#define DAC_DOR2			MMIO32(DAC_BASE + 0x30)
+
+
+/* --- DAC_CR values ------------------------------------------------------- */
+
+/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
+/* doesn't exist in most members of the stm32f1 family */
+#define DAC_CR_DMAUDRIE2		(1 << 29)
+
+/* DMAEN2: DAC channel2 DMA enable */
+#define DAC_CR_DMAEN2			(1 << 28)
+
+/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
+/* DAC_CR_MAMP2_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP2_SHIFT		24
+#define DAC_CR_MAMP2_1			(0x0 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_2			(0x1 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_3			(0x2 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_4			(0x3 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_5			(0x4 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_6			(0x5 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_7			(0x6 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_8			(0x7 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_9			(0x8 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_10			(0x9 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_11			(0xA << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_12			(0xB << DAC_CR_MAMP2_SHIFT)
+
+/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ */
+#define DAC_CR_WAVE2_SHIFT		22
+#define DAC_CR_WAVE2_DIS		(0x0 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_NOISE		(0x1 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_TRI		(0x2 << DAC_CR_WAVE2_SHIFT)
+
+/* TSEL2[2:0]: DAC channel2 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event
+ * T8: Timer 8 TRGO event
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL2_SHIFT		19
+#define DAC_CR_TSEL2_T6			(0x0 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T3			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T8			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T7			(0x2 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T5			(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T15		(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T2			(0x4 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T4			(0x5 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_E9			(0x6 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_SW			(0x7 << DAC_CR_TSEL2_SHIFT)
+
+/* TEN2: DAC channel2 trigger enable */
+#define DAC_CR_TEN2			(1 << 18)
+
+/* BOFF2: DAC channel2 output buffer disable */
+#define DAC_CR_BOFF2			(1 << 17)
+
+/* EN2: DAC channel2 enable */
+#define DAC_CR_EN2			(1 << 16)
+
+/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
+/* doesn't exist in most members of the stm32f1 family */
+#define DAC_CR_DMAUDRIE1	(1 << 13)
+
+/* DMAEN1: DAC channel1 DMA enable */
+#define DAC_CR_DMAEN1			(1 << 12)
+
+/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
+/* DAC_CR_MAMP1_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP1_SHIFT		8
+#define DAC_CR_MAMP1_1			(0x0 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_2			(0x1 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_3			(0x2 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_4			(0x3 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_5			(0x4 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_6			(0x5 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_7			(0x6 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_8			(0x7 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_9			(0x8 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_10			(0x9 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_11			(0xA << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_12			(0xB << DAC_CR_MAMP1_SHIFT)
+
+/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ */
+#define DAC_CR_WAVE1_SHIFT		6
+#define DAC_CR_WAVE1_DIS		(0x0 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_NOISE		(0x1 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_TRI		(0x2 << DAC_CR_WAVE1_SHIFT)
+
+/* TSEL1[2:0]: DAC channel1 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event in connectivity line devices
+ * T8: Timer 8 TRGO event in high-density and XL-density devices
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL1_SHIFT		3
+#define DAC_CR_TSEL1_T6			(0x0 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T3			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T8			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T7			(0x2 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T5			(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T15		(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T2			(0x4 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T4			(0x5 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_E9			(0x6 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_SW			(0x7 << DAC_CR_TSEL1_SHIFT)
+
+/* TEN1: DAC channel1 trigger enable */
+#define DAC_CR_TEN1			(1 << 2)
+
+/* BOFF1: DAC channel1 output buffer disable */
+#define DAC_CR_BOFF1			(1 << 1)
+
+/* EN1: DAC channel1 enable */
+#define DAC_CR_EN1			(1 << 0)
+
+
+/* --- DAC_SWTRIGR values -------------------------------------------------- */
+
+/* SWTRIG2: DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIG2		(1 << 1)
+
+/* SWTRIG1: DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG1		(1 << 0)
+
+
+/* --- DAC_DHR12R1 values -------------------------------------------------- */
+#define DAC_DHR12R1_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12R1_DACC1DHR_MSK	(0x0FFF << 0)
+
+
+/* --- DAC_DHR12L1 values -------------------------------------------------- */
+#define DAC_DHR12L1_DACC1DHR_LSB	(1 << 4)
+#define DAC_DHR12L1_DACC1DHR_MSK	(0x0FFF << 4)
+
+
+/* --- DAC_DHR8R1 values --------------------------------------------------- */
+#define DAC_DHR8R1_DACC1DHR_LSB		(1 << 0)
+#define DAC_DHR8R1_DACC1DHR_MSK		(0x00FF << 0)
+
+
+/* --- DAC_DHR12R2 values -------------------------------------------------- */
+#define DAC_DHR12R2_DACC2DHR_LSB	(1 << 0)
+#define DAC_DHR12R2_DACC2DHR_MSK	(0x00FFF << 0)
+
+
+/* --- DAC_DHR12L2 values -------------------------------------------------- */
+#define DAC_DHR12L2_DACC2DHR_LSB	(1 << 4)
+#define DAC_DHR12L2_DACC2DHR_MSK	(0x0FFF << 4)
+
+
+/* --- DAC_DHR8R2 values --------------------------------------------------- */
+#define DAC_DHR8R2_DACC2DHR_LSB		(1 << 0)
+#define DAC_DHR8R2_DACC2DHR_MSK		(0x00FF << 0)
+
+
+/* --- DAC_DHR12RD values -------------------------------------------------- */
+#define DAC_DHR12RD_DACC2DHR_LSB	(1 << 16)
+#define DAC_DHR12RD_DACC2DHR_MSK	(0x0FFF << 16)
+#define DAC_DHR12RD_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12RD_DACC1DHR_MSK	(0x0FFF << 0)
+
+
+/* --- DAC_DHR12LD values -------------------------------------------------- */
+#define DAC_DHR12LD_DACC2DHR_LSB	(1 << 16)
+#define DAC_DHR12LD_DACC2DHR_MSK	(0x0FFF << 20)
+#define DAC_DHR12LD_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12LD_DACC1DHR_MSK	(0x0FFF << 4)
+
+
+/* --- DAC_DHR8RD values --------------------------------------------------- */
+#define DAC_DHR8RD_DACC2DHR_LSB		(1 << 8)
+#define DAC_DHR8RD_DACC2DHR_MSK		(0x00FF << 8)
+#define DAC_DHR8RD_DACC1DHR_LSB		(1 << 0)
+#define DAC_DHR8RD_DACC1DHR_MSK		(0x00FF << 0)
+
+
+/* --- DAC_DOR1 values ----------------------------------------------------- */
+#define DAC_DOR1_DACC1DOR_LSB		(1 << 0)
+#define DAC_DOR1_DACC1DOR_MSK		(0x0FFF << 0)
+
+
+/* --- DAC_DOR2 values ----------------------------------------------------- */
+#define DAC_DOR2_DACC2DOR_LSB		(1 << 0)
+#define DAC_DOR2_DACC2DOR_MSK		(0x0FFF << 0)
+
+
+/* --- Function prototypes ------------------------------------------------- */
+
+
+/* TODO */
+
+
+#endif

include/libopencm3/stm32/f1/dma.h

@@ -252,14 +252,14 @@
 #define DMA_CCR_MSIZE_8BIT		(0x0 << 10)
 #define DMA_CCR_MSIZE_16BIT		(0x1 << 10)
 #define DMA_CCR_MSIZE_32BIT		(0x2 << 10)
-#define DMA_CCR_MSIZE_MASK		(0x2 << 10)
+#define DMA_CCR_MSIZE_MASK		(0x3 << 10)
 #define DMA_CCR_MSIZE_SHIFT		10
 
 /* PSIZE[9:8]: Peripheral size */
 #define DMA_CCR_PSIZE_8BIT		(0x0 << 8)
 #define DMA_CCR_PSIZE_16BIT		(0x1 << 8)
 #define DMA_CCR_PSIZE_32BIT		(0x2 << 8)
-#define DMA_CCR_PSIZE_MASK		(0x2 << 8)
+#define DMA_CCR_PSIZE_MASK		(0x3 << 8)
 #define DMA_CCR_PSIZE_SHIFT		8
 
 /* MINC: Memory increment mode */

include/libopencm3/stm32/f1/rtc.h

@@ -23,6 +23,7 @@
 #include <libopencm3/stm32/memorymap.h>
 #include <libopencm3/cm3/common.h>
 #include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/f1/rcc.h>
 
 /* --- RTC registers ------------------------------------------------------- */
 

include/libopencm3/stm32/timer.h

@@ -533,8 +533,8 @@
 /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
  * TIMx_CCER). */
 #define TIM_CCMR1_CC1S_OUT		(0x0 << 0)
-#define TIM_CCMR1_CC1S_IN_TI2		(0x1 << 0)
+#define TIM_CCMR1_CC1S_IN_TI2		(0x2 << 0)
-#define TIM_CCMR1_CC1S_IN_TI1		(0x2 << 0)
+#define TIM_CCMR1_CC1S_IN_TI1		(0x1 << 0)
 #define TIM_CCMR1_CC1S_IN_TRC		(0x3 << 0)
 #define TIM_CCMR1_CC1S_MASK		(0x3 << 0)
 
@@ -851,14 +851,66 @@ enum tim_oc_mode {
 	TIM_OCM_PWM2,
 };
 
+/* Input Capture channel designators */
+enum tim_ic_id {
+	TIM_IC1,
+	TIM_IC2,
+	TIM_IC3,
+	TIM_IC4,
+};
+
+/* Input Capture input filter */
+enum tim_ic_filter {
+	TIM_IC_OFF,
+	TIM_IC_CK_INT_N_2,
+	TIM_IC_CK_INT_N_4,
+	TIM_IC_CK_INT_N_8,
+	TIM_IC_DTF_DIV_2_N_6,
+	TIM_IC_DTF_DIV_2_N_8,
+	TIM_IC_DTF_DIV_4_N_6,
+	TIM_IC_DTF_DIV_4_N_8,
+	TIM_IC_DTF_DIV_8_N_6,
+	TIM_IC_DTF_DIV_8_N_8,
+	TIM_IC_DTF_DIV_16_N_5,
+	TIM_IC_DTF_DIV_16_N_6,
+	TIM_IC_DTF_DIV_16_N_8,
+	TIM_IC_DTF_DIV_32_N_5,
+	TIM_IC_DTF_DIV_32_N_6,
+	TIM_IC_DTF_DIV_32_N_8,
+};
+
+/* Input Capture input prescaler */
+enum tim_ic_psc {
+	TIM_IC_PSC_OFF,
+	TIM_IC_PSC_2,
+	TIM_IC_PSC_4,
+	TIM_IC_PSC_8,
+};
+
+/* Input Capture input prescaler */
+enum tim_ic_input {
+	TIM_IC_OUT = 0,
+	TIM_IC_IN_TI1 = 1,
+	TIM_IC_IN_TI2 = 2,
+	TIM_IC_IN_TRC = 3,
+	TIM_IC_IN_TI3 = 5,
+	TIM_IC_IN_TI4 = 6,
+};
+
+/* Input Capture input prescaler */
+enum tim_ic_pol {
+	TIM_IC_RISING,
+	TIM_IC_FALLING,
+};
+
 /* --- TIM functions ------------------------------------------------------- */
 void timer_reset(u32 timer_peripheral);
 void timer_enable_irq(u32 timer_peripheral, u32 irq);
 void timer_disable_irq(u32 timer_peripheral, u32 irq);
 bool timer_get_flag(u32 timer_peripheral, u32 flag);
 void timer_clear_flag(u32 timer_peripheral, u32 flag);
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
-		    u8 alignment, u8 direction);
+		    u32 alignment, u32 direction);
 void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
 void timer_enable_preload(u32 timer_peripheral);
 void timer_disable_preload(u32 timer_peripheral);
@@ -918,4 +970,17 @@ void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
 void timer_generate_event(u32 timer_peripheral, u32 event);
 u32 timer_get_counter(u32 timer_peripheral);
 
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
+void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in);
+void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
+void timer_ic_enable(u32 timer, enum tim_ic_id ic);
+void timer_ic_disable(u32 timer, enum tim_ic_id ic);
+
+void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt);
+void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
+void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
+void timer_slave_set_mode(u32 timer, u8 mode);
+void timer_slave_set_trigger(u32 timer, u8 trigger);
+
 #endif

lib/stm32/f1/libopencm3_stm32f1.ld

@@ -38,36 +38,43 @@ SECTIONS
 		. = ALIGN(4);
 		*(.rodata*)	/* Read-only data */
 		. = ALIGN(4);
-	} >rom
-
-	/* exception index - required due to libgcc.a issuing /0 exceptions */
-	__exidx_start = .;
-	.ARM.exidx : {
-		   *(.ARM.exidx*)
-	} > rom
-	__exidx_end = .;
-
-
 		_etext = .;
+	} >rom
 
-	.data : {
+	/*
+	* Another section used by C++ stuff, appears when using newlib with
+	* 64bit (long long) printf support
+	*/
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
+
+	. = ORIGIN(ram);
+
+	.data : AT (__exidx_end) {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
 		_edata = .;
-	} >ram AT >rom
+	} >ram
 
 	.bss : {
 		*(.bss*)	/* Read-write zero initialized data */
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = .;
-	} >ram
+	} >ram AT >rom
 
-	/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
+	/*
-	.ARM.extab : {
+	 * The .eh_frame section appears to be used for C++ exception handling.
-		*(.ARM.extab*)
+	 * You may need to fix this if you're using C++.
-	} >ram
+	 */
+	/DISCARD/ : { *(.eh_frame) }
 
 	. = ALIGN(4);
 	end = .;

lib/stm32/f1/rtc.c

@@ -99,14 +99,13 @@ void rtc_enter_config_mode(void)
 
 void rtc_exit_config_mode(void)
 {
-	/* u32 reg32; */
+	u32 reg32;
 
 	/* Exit configuration mode. */
 	RTC_CRL &= ~RTC_CRL_CNF;
 
 	/* Wait until the RTOFF bit is 1 (our RTC register write finished). */
-	/* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */
+	while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
-	/* TODO: Unnecessary since we poll the bit on config entry(?) */
 }
 
 void rtc_set_alarm_time(u32 alarm_time)

lib/stm32/f1/timer.c

@@ -118,8 +118,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
 	TIM_SR(timer_peripheral) &= ~flag;
 }
 
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
-		    u8 alignment, u8 direction)
+		    u32 alignment, u32 direction)
 {
 	u32 cr1;
 
@@ -914,3 +914,128 @@ u32 timer_get_counter(u32 timer_peripheral)
 {
 	return TIM_CNT(timer_peripheral);
 }
+
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
+{
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
+		TIM_CCMR1(timer) |= flt << 4;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
+		TIM_CCMR1(timer) |= flt << 12;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
+		TIM_CCMR2(timer) |= flt << 4;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
+		TIM_CCMR2(timer) |= flt << 12;
+		break;
+	}
+}
+
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
+{
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
+		TIM_CCMR1(timer) |= psc << 2;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
+		TIM_CCMR1(timer) |= psc << 10;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
+		TIM_CCMR2(timer) |= psc << 4;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
+		TIM_CCMR2(timer) |= psc << 10;
+		break;
+	}
+}
+
+void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
+{
+	in &= 3;
+
+	if (((ic == TIM_IC2) || (ic == TIM_IC4)) &&
+	    ((in == TIM_IC_IN_TI1) || (in = TIM_IC_IN_TI2))) {
+		/* Input select bits are flipped for these combinations */
+		in ^= 3;
+	}
+	
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_CC1S_MASK;
+		TIM_CCMR1(timer) |= in;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_CC2S_MASK;
+		TIM_CCMR1(timer) |= in << 8;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_CC3S_MASK;
+		TIM_CCMR2(timer) |= in;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_CC4S_MASK;
+		TIM_CCMR2(timer) |= in << 8;
+		break;
+	}
+}
+
+void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol)
+{
+	if (pol)
+		TIM_CCER(timer) |= (0x2 << (ic * 4));
+	else
+		TIM_CCER(timer) &= ~(0x2 << (ic * 4));
+}
+
+void timer_ic_enable(u32 timer, enum tim_ic_id ic)
+{
+	TIM_CCER(timer) |= (0x1 << (ic * 4));
+}
+
+void timer_ic_disable(u32 timer, enum tim_ic_id ic)
+{
+	TIM_CCER(timer) &= ~(0x1 << (ic * 4));
+}
+
+void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_ETF_MASK;
+	TIM_SMCR(timer) |= flt << 8;
+}
+
+void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_ETPS_MASK;
+	TIM_SMCR(timer) |= psc << 12;
+}
+
+void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol)
+{
+	if (pol)
+		TIM_SMCR(timer) |= TIM_SMCR_ETP;
+	else
+		TIM_SMCR(timer) &= ~TIM_SMCR_ETP;
+}
+
+void timer_slave_set_mode(u32 timer, u8 mode)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_SMS_MASK;
+	TIM_SMCR(timer) |= mode;
+}
+
+void timer_slave_set_trigger(u32 timer, u8 trigger)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_TS_MASK;
+	TIM_SMCR(timer) |= trigger;
+}
+

lib/stm32/f1/vector.c

@@ -20,7 +20,7 @@
 #define WEAK __attribute__ ((weak))
 
 /* Symbols exported by the linker script(s). */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
 
 void main(void);
 void reset_handler(void);
@@ -197,7 +197,7 @@ void reset_handler(void)
 
 	__asm__("MSR msp, %0" : : "r"(&_stack));
 
-	for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+	for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
 		*dest = *src;
 
 	while (dest < &_ebss)

lib/stm32/f2/libopencm3_stm32f2.ld

@@ -38,36 +38,43 @@ SECTIONS
 		. = ALIGN(4);
 		*(.rodata*)	/* Read-only data */
 		. = ALIGN(4);
-	} >rom
-
-	/* exception index - required due to libgcc.a issuing /0 exceptions */
-	__exidx_start = .;
-	.ARM.exidx : {
-		   *(.ARM.exidx*)
-	} > rom
-	__exidx_end = .;
-
-
 		_etext = .;
+	} >rom
 
-	.data : {
+	/*
+	* Another section used by C++ stuff, appears when using newlib with
+	* 64bit (long long) printf support
+	*/
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
+
+	. = ORIGIN(ram);
+
+	.data : AT (__exidx_end) {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
 		_edata = .;
-	} >ram AT >rom
+	} >ram
 
 	.bss : {
 		*(.bss*)	/* Read-write zero initialized data */
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = .;
-	} >ram
+	} >ram AT >rom
 
-	/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
+	/*
-	.ARM.extab : {
+	 * The .eh_frame section appears to be used for C++ exception handling.
-		*(.ARM.extab*)
+	 * You may need to fix this if you're using C++.
-	} >ram
+	 */
+	/DISCARD/ : { *(.eh_frame) }
 
 	. = ALIGN(4);
 	end = .;

lib/stm32/f2/timer.c

@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
 	TIM_SR(timer_peripheral) &= ~flag;
 }
 
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
-		    u8 alignment, u8 direction)
+		    u32 alignment, u32 direction)
 {
 	u32 cr1;
 

lib/stm32/f2/vector.c

@@ -21,7 +21,7 @@
 #define WEAK __attribute__ ((weak))
 
 /* Symbols exported by the linker script(s): */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
 
 void main(void);
 void reset_handler(void);
@@ -224,7 +224,7 @@ void reset_handler(void)
 
 	__asm__("MSR msp, %0" : : "r"(&_stack));
 
-	for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+	for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
 		*dest = *src;
 
 	while (dest < &_ebss)

lib/stm32/f4/timer.c

@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
 	TIM_SR(timer_peripheral) &= ~flag;
 }
 
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
-		    u8 alignment, u8 direction)
+		    u32 alignment, u32 direction)
 {
 	u32 cr1;