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Merge commit 'e535f53981da1fe80137504c761bc854ea8be356' into sam-update

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Jason Kotzin 2022-08-10 22:30:11 -07:00
commit 2a792399ca
1 changed files with 107 additions and 71 deletions
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178
src/target/ch32f1.c
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@ -1,14 +1,37 @@
/* /*
* This file is part of the Black Magic Debug project. * This file is part of the Black Magic Debug project.
* *
* Copyright (C) 2022 Black Sphere Technologies Ltd. * Copyright (C) 2011 Black Sphere Technologies Ltd.
* See CH32 Sample code from WCH StdPeriphLib_CH32F1/Examples/FLASH/FLASH_Program * Written by Gareth McMullin <gareth@blacksphere.co.nz>
* *
* The CH32 seems to like the EOP bit to be cleared at the end of erase/flash operation * This program is free software: you can redistribute it and/or modify
* The following code works fine in BMP hosted mode * it under the terms of the GNU General Public License as published by
* It does NOT work with a real BMP, only the first 128 bytes block is successfully written * the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
/* This file implements CH32F1xx target specific functions.
The ch32 flash is rather slow so this code is using the so called fast mode (ch32 specific).
128 bytes are copied to a write buffer, then the write buffer is committed to flash
/!\ There is some sort of bus stall/bus arbitration going on that does NOT work when
programmed through SWD/jtag
The workaround is to wait a few cycles before filling the write buffer. This is performed by reading the flash a few times
*/
#include "general.h"
#include "target.h"
#include "target_internal.h"
#include "cortexm.h"
#if PC_HOSTED == 1 #if PC_HOSTED == 1
#define DEBUG_CH DEBUG_INFO #define DEBUG_CH DEBUG_INFO
#define ERROR_CH DEBUG_WARN #define ERROR_CH DEBUG_WARN
@ -17,27 +40,48 @@
#define ERROR_CH DEBUG_WARN //DEBUG_WARN #define ERROR_CH DEBUG_WARN //DEBUG_WARN
#endif #endif
extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff
static int ch32f1_flash_erase(struct target_flash *f, static int ch32f1_flash_erase(struct target_flash *f,
target_addr addr, size_t len); target_addr addr, size_t len);
static int ch32f1_flash_write(struct target_flash *f, static int ch32f1_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len); target_addr dest, const void *src, size_t len);
#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x
// these are common with stm32f1/gd32f1/...
#define FPEC_BASE 0x40022000
#define FLASH_ACR (FPEC_BASE+0x00)
#define FLASH_KEYR (FPEC_BASE+0x04)
#define FLASH_SR (FPEC_BASE+0x0C)
#define FLASH_CR (FPEC_BASE+0x10)
#define FLASH_AR (FPEC_BASE+0x14)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_SR_BSY (1 << 0)
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
#define SR_ERROR_MASK 0x14
#define SR_EOP 0x20
#define DBGMCU_IDCODE 0xE0042000
#define FLASHSIZE 0x1FFFF7E0
// these are specific to ch32f1
#define FLASH_MAGIC (FPEC_BASE+0x34)
#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x
#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock
#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program
#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase
#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load
#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset
#define FLASH_SR_EOP (1<<5) // End of programming
#define FLASH_BEGIN_ADDRESS_CH32 0x8000000
#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock
#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program
#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase
#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load
#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset
#define FLASH_SR_EOP (1<<5) // End of programming
#define FLASH_BEGIN_ADDRESS_CH32 0x8000000
#define FLASH_MAGIC (FPEC_BASE+0x34)
static volatile uint32_t magic,sr,ct;
/** /**
\fn ch32f1_add_flash \fn ch32f1_add_flash
\brief "fast" flash driver for CH32F10x chips \brief "fast" flash driver for CH32F10x chips
*/ */
static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t erasesize) static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t erasesize)
{ {
@ -57,42 +101,38 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
target_add_flash(t, f); target_add_flash(t, f);
} }
#define WAIT_BUSY() do { \
sr = target_mem_read32(t, FLASH_SR); \
if(target_check_error(t)) { \
ERROR_CH("ch32f1 flash write: comm error\n"); \
#define WAIT_BUSY() do { \ return -1; \
sr = target_mem_read32(t, FLASH_SR); \ } \
if(target_check_error(t)) { \ } while (sr & FLASH_SR_BSY);
ERROR_CH("ch32f1 flash write: comm error\n"); \
return -1; \
} \
} while (sr & FLASH_SR_BSY);
#define WAIT_EOP() do { \ #define WAIT_EOP() do { \
sr = target_mem_read32(t, FLASH_SR); \ sr = target_mem_read32(t, FLASH_SR); \
if(target_check_error(t)) { \ if(target_check_error(t)) { \
ERROR_CH("ch32f1 flash write: comm error\n"); \ ERROR_CH("ch32f1 flash write: comm error\n"); \
return -1; \ return -1; \
} \ } \
} while (!(sr & FLASH_SR_EOP)); } while (!(sr & FLASH_SR_EOP));
#define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP) #define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP)
#define SET_CR(bit) { ct = target_mem_read32(t, FLASH_CR); \ #define SET_CR(bit) { ct = target_mem_read32(t, FLASH_CR); \
ct|=(bit); \ ct|=(bit); \
target_mem_write32(t, FLASH_CR, ct);} target_mem_write32(t, FLASH_CR, ct);}
#define CLEAR_CR(bit) {ct = target_mem_read32(t, FLASH_CR); \ #define CLEAR_CR(bit) {ct = target_mem_read32(t, FLASH_CR); \
ct&=~(bit); \ ct&=~(bit); \
target_mem_write32(t, FLASH_CR, ct);} target_mem_write32(t, FLASH_CR, ct);}
// Which one is the right value ? // Which one is the right value ?
#define MAGIC_WORD 0x100 #define MAGIC_WORD 0x100
// #define MAGIC_WORD 0x100 // #define MAGIC_WORD 0x1000
#define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \ #define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \
target_mem_write32(t, FLASH_MAGIC , magic); } target_mem_write32(t, FLASH_MAGIC , magic); }
/** /**
\fn ch32f1_flash_unlock \fn ch32f1_flash_unlock
@ -108,8 +148,7 @@ static int ch32f1_flash_unlock(target *t)
target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1); target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1);
target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2); target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2);
uint32_t cr = target_mem_read32(t, FLASH_CR); uint32_t cr = target_mem_read32(t, FLASH_CR);
if (cr & FLASH_CR_FLOCK_CH32) if (cr & FLASH_CR_FLOCK_CH32){
{
ERROR_CH("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr); ERROR_CH("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr);
return -1; return -1;
} }
@ -117,6 +156,7 @@ static int ch32f1_flash_unlock(target *t)
} }
static int ch32f1_flash_lock(target *t) static int ch32f1_flash_lock(target *t)
{ {
volatile uint32_t ct;
DEBUG_CH("CH32: flash lock \n"); DEBUG_CH("CH32: flash lock \n");
SET_CR(FLASH_CR_LOCK); SET_CR(FLASH_CR_LOCK);
return 0; return 0;
@ -124,7 +164,7 @@ static int ch32f1_flash_lock(target *t)
/** /**
\brief identify the ch32f1 chip \brief identify the ch32f1 chip
Actually grab all cortex m3 with designer = arm not caught earlier... Actually grab all cortex m3 with designer = arm not caught earlier...
*/ */
bool ch32f1_probe(target *t) bool ch32f1_probe(target *t)
@ -143,17 +183,13 @@ bool ch32f1_probe(target *t)
return false; return false;
} }
uint32_t signature = target_mem_read32(t, FLASHSIZE);
uint32_t signature= target_mem_read32(t, FLASHSIZE); uint32_t flashSize = signature & 0xFFFF;
uint32_t flashSize=signature & 0xFFFF;
target_add_ram(t, 0x20000000, 0x5000); target_add_ram(t, 0x20000000, 0x5000);
ch32f1_add_flash(t, FLASH_BEGIN_ADDRESS_CH32, flashSize*1024, 128); ch32f1_add_flash(t, FLASH_BEGIN_ADDRESS_CH32, flashSize*1024, 128);
target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD/VL-LD/VL-MD"); target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD/VL-LD/VL-MD");
t->driver = "CH32F1 medium density (stm32f1 clone)"; t->driver = "CH32F1 medium density (stm32f1 clone)";
// make sure we have 2 wait states
//target_mem_write32(t, FLASH_ACR,2);
return true; return true;
} }
/** /**
@ -162,12 +198,10 @@ bool ch32f1_probe(target *t)
*/ */
int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len) int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
{ {
volatile uint32_t ct, sr, magic;
target *t = f->t; target *t = f->t;
DEBUG_CH("CH32: flash erase \n"); DEBUG_CH("CH32: flash erase \n");
// Make sure we have 2 wait states, prefetch disabled
//target_mem_write32(t, FLASH_ACR , 2);
if (ch32f1_flash_unlock(t)) { if (ch32f1_flash_unlock(t)) {
ERROR_CH("CH32: Unlock failed\n"); ERROR_CH("CH32: Unlock failed\n");
return -1; return -1;
@ -209,12 +243,11 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
static bool ch32f1_wait_flash_ready(target *t,uint32_t adr) static bool ch32f1_wait_flash_ready(target *t,uint32_t adr)
{ {
uint32_t ff; uint32_t ff;
for(int i=0;i<32;i++) { for(int i = 0; i < 32; i++) {
ff=target_mem_read32(t,adr); ff = target_mem_read32(t,adr);
} }
if(ff!=0xffffffffUL) { if(ff != 0xffffffffUL) {
ERROR_CH("ch32f1 Not erased properly at %x or flash access issue\n",adr); ERROR_CH("ch32f1 Not erased properly at %x or flash access issue\n",adr);
return false; return false;
} }
@ -227,8 +260,9 @@ static bool ch32f1_wait_flash_ready(target *t,uint32_t adr)
static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t offset) static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t offset)
{ {
const uint32_t *ss=(const uint32_t *)(src+offset); volatile uint32_t ct, sr, magic;
uint32_t dd=dest+offset; const uint32_t *ss = (const uint32_t *)(src+offset);
uint32_t dd = dest+offset;
SET_CR(FLASH_CR_FTPG_CH32); SET_CR(FLASH_CR_FTPG_CH32);
target_mem_write32(t, dd+0,ss[0]); target_mem_write32(t, dd+0,ss[0]);
@ -248,6 +282,7 @@ static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t of
*/ */
int ch32f1_buffer_clear(target *t) int ch32f1_buffer_clear(target *t)
{ {
volatile uint32_t ct,sr;
SET_CR(FLASH_CR_FTPG_CH32); // Fast page program 4- SET_CR(FLASH_CR_FTPG_CH32); // Fast page program 4-
SET_CR(FLASH_CR_BUF_RESET_CH32); // BUF_RESET 5- SET_CR(FLASH_CR_BUF_RESET_CH32); // BUF_RESET 5-
WAIT_BUSY(); // 6- WAIT_BUSY(); // 6-
@ -260,8 +295,9 @@ int ch32f1_buffer_clear(target *t)
*/ */
static int ch32f1_flash_write(struct target_flash *f, static int ch32f1_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len) target_addr dest, const void *src, size_t len)
{ {
volatile uint32_t ct, sr, magic;
target *t = f->t; target *t = f->t;
size_t length = len; size_t length = len;
#ifdef CH32_VERIFY #ifdef CH32_VERIFY
@ -270,7 +306,7 @@ static int ch32f1_flash_write(struct target_flash *f,
#endif #endif
DEBUG_CH("CH32: flash write 0x%x ,size=%d\n",dest,len); DEBUG_CH("CH32: flash write 0x%x ,size=%d\n",dest,len);
while(length>0) while(length > 0)
{ {
if(ch32f1_flash_unlock(t)) { if(ch32f1_flash_unlock(t)) {
ERROR_CH("ch32f1 cannot fast unlock\n"); ERROR_CH("ch32f1 cannot fast unlock\n");
@ -284,7 +320,7 @@ static int ch32f1_flash_write(struct target_flash *f,
if(!ch32f1_wait_flash_ready(t,dest)) { if(!ch32f1_wait_flash_ready(t,dest)) {
return -1; return -1;
} }
for(int i=0;i<8;i++) { for(int i = 0; i < 8; i++) {
if(ch32f1_upload(t,dest,src, 16*i)) { if(ch32f1_upload(t,dest,src, 16*i)) {
ERROR_CH("Cannot upload to buffer\n"); ERROR_CH("Cannot upload to buffer\n");
return -1; return -1;
@ -301,12 +337,12 @@ static int ch32f1_flash_write(struct target_flash *f,
MAGIC((dest)); MAGIC((dest));
// next // next
if(length>128) if(length > 128)
length-=128; length -=128;
else else
length=0; length = 0;
dest+=128; dest += 128;
src+=128; src += 128;
sr = target_mem_read32(t, FLASH_SR); // 13 sr = target_mem_read32(t, FLASH_SR); // 13
ch32f1_flash_lock(t); ch32f1_flash_lock(t);
@ -318,8 +354,8 @@ static int ch32f1_flash_write(struct target_flash *f,
} }
#ifdef CH32_VERIFY #ifdef CH32_VERIFY
DEBUG_CH("Verifying\n"); DEBUG_CH("Verifying\n");
size_t i=0; size_t i = 0;
for(i=0;i<len;i+=4) for(i = 0; i < len; i+= 4)
{ {
uint32_t mem=target_mem_read32(t, orgDest+i); uint32_t mem=target_mem_read32(t, orgDest+i);
uint32_t mem2=*(uint32_t *)(orgSrc+i); uint32_t mem2=*(uint32_t *)(orgSrc+i);