stm32f3: i2c support now in f3 directory.
Very few functions can be shared (~ 3). A possible solutions is to move i2c_common_all to i2c_common_f124, create i2c_common_all and move f3/i2c to i2c_common_f3. Who agrees?
This commit is contained in:
Federico Ruiz Ugalde
Piotr Esden-Tempski
parent
8f3675fbfd
commit
4673348ff7
@ -32,7 +32,424 @@ LGPL License Terms @ref lgpl_license
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#define LIBOPENCM3_I2C_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/i2c_common_all.h>
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/* --- Convenience macros -------------------------------------------------- */
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/* I2C register base addresses (for convenience) */
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/****************************************************************************/
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/** @defgroup i2c_reg_base I2C register base address
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@ingroup i2c_defines
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@{*/
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#define I2C1 I2C1_BASE
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#define I2C2 I2C2_BASE
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/**@}*/
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/* --- I2C registers ------------------------------------------------------- */
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/* Control register 1 (I2Cx_CR1) */
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#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
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#define I2C1_CR1 I2C_CR1(I2C1)
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#define I2C2_CR1 I2C_CR1(I2C2)
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/* Control register 2 (I2Cx_CR2) */
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#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
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#define I2C1_CR2 I2C_CR2(I2C1)
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#define I2C2_CR2 I2C_CR2(I2C2)
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/* Own address register 1 (I2Cx_OAR1) */
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#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
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#define I2C1_OAR1 I2C_OAR1(I2C1)
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#define I2C2_OAR1 I2C_OAR1(I2C2)
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/* Own address register 2 (I2Cx_OAR2) */
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#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
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#define I2C1_OAR2 I2C_OAR2(I2C1)
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#define I2C2_OAR2 I2C_OAR2(I2C2)
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/* Timing register (I2Cx_TIMINGR) */
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#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10)
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#define I2C1_TIMINGR I2C_TIMINGR(I2C1)
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#define I2C2_TIMINGR I2C_TIMINGR(I2C2)
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/* Timeout register (I2Cx_TIMEOUTR) */
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#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14)
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#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1)
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#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2)
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/* Interrupt and Status register (I2Cx_ISR) */
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#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18)
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#define I2C1_ISR I2C_ISR(I2C1)
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#define I2C2_ISR I2C_ISR(I2C2)
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/* Interrupt clear register (I2Cx_ICR) */
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#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C)
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#define I2C1_ICR I2C_ICR(I2C1)
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#define I2C2_ICR I2C_ICR(I2C2)
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/* PEC register (I2Cx_PECR) */
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#define I2C_PECR(i2c_base) MMIO32(i2c_base + 0x20)
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#define I2C1_PECR I2C_PECR(I2C1)
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#define I2C2_PECR I2C_PECR(I2C2)
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/* Receive data register (I2Cx_RXDR) */
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#define I2C_RXDR(i2c_base) MMIO32(i2c_base + 0x24)
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#define I2C1_RXDR I2C_RXDR(I2C1)
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#define I2C2_RXDR I2C_RXDR(I2C2)
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/* Transmit data register (I2Cx_TXDR) */
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#define I2C_TXDR(i2c_base) MMIO32(i2c_base + 0x28)
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#define I2C1_TXDR I2C_TXDR(I2C1)
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#define I2C2_TXDR I2C_TXDR(I2C2)
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/* --- I2Cx_CR1 values ----------------------------------------------------- */
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/* PECEN: PEC enable */
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#define I2C_CR1_PECEN (1 << 23)
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/* ALERTEN: SMBus alert enable */
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#define I2C_CR1_ALERTEN (1 << 22)
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/* SMBDEN: SMBus Device Default address enable */
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#define I2C_CR1_SMBDEN (1 << 21)
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/* SMBHEN: SMBus Host address enable */
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#define I2C_CR1_SMBHEN (1 << 20)
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/* GCEN: General call enable */
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#define I2C_CR1_GCEN (1 << 19)
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/* WUPEN: Wakeup from STOP enable */
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#define I2C_CR1_WUPEN (1 << 18)
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/* NOSTRETCH: Clock stretching disable */
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#define I2C_CR1_NOSTRETCH (1 << 17)
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/* SBC: Slave byte control */
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#define I2C_CR1_SBC (1 << 16)
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/* RXDMAEN: DMA reception requests enable */
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#define I2C_CR1_RXDMAEN (1 << 15)
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/* TXDMAEN: DMA transmission requests enable */
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#define I2C_CR1_TXDMAEN (1 << 14)
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/* ANFOFF: Analog noise filter OFF */
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#define I2C_CR1_ANFOFF (1 << 12)
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/* DNF[3:0]: Digital noise filter */
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#define I2C_CR1_DNF_DISABLED (0x0 << 8)
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#define I2C_CR1_DNF_UP_1_TI2CCLK (0x1 << 8)
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#define I2C_CR1_DNF_UP_2_TI2CCLK (0x2 << 8)
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#define I2C_CR1_DNF_UP_3_TI2CCLK (0x3 << 8)
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#define I2C_CR1_DNF_UP_4_TI2CCLK (0x4 << 8)
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#define I2C_CR1_DNF_UP_5_TI2CCLK (0x5 << 8)
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#define I2C_CR1_DNF_UP_6_TI2CCLK (0x6 << 8)
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#define I2C_CR1_DNF_UP_7_TI2CCLK (0x7 << 8)
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#define I2C_CR1_DNF_UP_8_TI2CCLK (0x8 << 8)
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#define I2C_CR1_DNF_UP_9_TI2CCLK (0x9 << 8)
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#define I2C_CR1_DNF_UP_10_TI2CCLK (0xA << 8)
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#define I2C_CR1_DNF_UP_11_TI2CCLK (0xB << 8)
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#define I2C_CR1_DNF_UP_12_TI2CCLK (0xC << 8)
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#define I2C_CR1_DNF_UP_13_TI2CCLK (0xD << 8)
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#define I2C_CR1_DNF_UP_14_TI2CCLK (0xE << 8)
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#define I2C_CR1_DNF_UP_15_TI2CCLK (0xF << 8)
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#define I2C_CR1_DNF_MASK (0xF << 8)
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/* ERRIE: Error interrupts enable */
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#define I2C_CR1_ERRIE (1 << 7)
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/* TCIE: Transfer Complete interrupt enable */
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#define I2C_CR1_TCIE (1 << 6)
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/* STOPIE: STOP detection Interrupt enable */
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#define I2C_CR1_STOPIE (1 << 5)
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/* NACKIE: Not acknowledge received Interrupt enable */
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#define I2C_CR1_NACKIE (1 << 4)
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/* ADDRIE: Address match Interrupt enable (slave only) */
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#define I2C_CR1_DDRIE (1 << 3)
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/* RXIE: RX Interrupt enable */
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#define I2C_CR1_RXIE (1 << 2)
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/* TXIE: TX Interrupt enable */
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#define I2C_CR1_TXIE (1 << 1)
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/* PE: Peripheral enable */
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#define I2C_CR1_PE (1 << 0)
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/* --- I2Cx_CR2 values ----------------------------------------------------- */
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/* PECBYTE: Packet error checking byte */
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#define I2C_CR2_PECBYTE (1 << 26)
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/* AUTOEND: Automatic end mode (master mode) */
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#define I2C_CR2_AUTOEND (1 << 25)
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/* RELOAD: NBYTES reload mode */
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#define I2C_CR2_RELOAD (1 << 24)
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/* NBYTES[7:0]: Number of bytes (23,16) */
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#define I2C_CR2_NBYTES_SHIFT 16
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#define I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT)
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/* NACK: NACK generation (slave mode) */
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#define I2C_CR2_NACK (1 << 15)
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/* STOP: Stop generation (master mode) */
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#define I2C_CR2_STOP (1 << 14)
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/* START: Start generation */
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#define I2C_CR2_START (1 << 13)
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/* HEAD10R: 10-bit address header only read direction (master receiver mode) */
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#define I2C_CR2_HEAD10R (1 << 12)
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/* ADD10: 10-bit addressing mode (master mode) */
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#define I2C_CR2_ADD10 (1 << 11)
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/* RD_WRN: Transfer direction (master mode) */
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#define I2C_CR2_RD_WRN (1 << 10)
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#define I2C_CR2_SADD_7BIT_SHIFT 1
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#define I2C_CR2_SADD_10BIT_SHIFT 0
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#define I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT)
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#define I2C_CR2_SADD_10BIT_MASK 0x3FF
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/* --- I2Cx_OAR1 values ---------------------------------------------------- */
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/* OA1EN: Own Address 1 enable */
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#define I2C_OAR1_OA1EN_DISABLE (0x0 << 15)
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#define I2C_OAR1_OA1EN_ENABLE (0x1 <<15)
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/* OA1MODE Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1MODE (1 << 10)
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#define I2C_OAR1_OA1MODE_7BIT 0
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#define I2C_OAR1_OA1MODE_10BIT 1
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/* OA1[9:8]: Interface address */
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/* OA1[7:1]: Interface address */
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/* OA1[0]: Interface address */
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#define I2C_OAR1_OA1 (1 << 10)
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#define I2C_OAR1_OA1_7BIT 0
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#define I2C_OAR1_OA1_10BIT 1
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/* --- I2Cx_OAR2 values ---------------------------------------------------- */
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/* OA2EN: Own Address 2 enable */
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#define I2C_OAR2_OA2EN (1 << 15)
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/* OA2MSK[2:0]: Own Address 2 masks */
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#define I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8)
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#define I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8)
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/* OA2[7:1]: Interface address */
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/* --- I2Cx_TIMINGR values ---------------------------------------------------- */
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/* PRESC[3:0]: Timing prescaler (31,28) */
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#define I2C_TIMINGR_PRESC_SHIFT 28
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#define I2C_TIMINGR_PRESC_MASK (0xF << 28)
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/* SCLDEL[3:0]: Data setup time (23,20) */
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#define I2C_TIMINGR_SCLDEL_SHIFT 20
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#define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT)
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/* SDADEL[3:0]: Data hold time (19,16) */
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#define I2C_TIMINGR_SDADEL_SHIFT 16
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#define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT)
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/* SCLH[7:0]: SCL high period (master mode) (15,8) */
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#define I2C_TIMINGR_SCLH_SHIFT 8
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#define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT)
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/* SCLL[7:0]: SCL low period (master mode) (7,0) */
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#define I2C_TIMINGR_SCLL_SHIFT 0
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#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)
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/* --- I2Cx_TIEMOUTR values ---------------------------------------------------- */
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/* TEXTEN: Extended clock timeout enable */
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#define I2C_TIEMOUTR_TEXTEN (1 << 31)
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//Not clear yet.
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/* TIMEOUTB[11:0]: Bus timeout B */
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/* TIMOUTEN: Clock timeout enable */
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#define I2C_TIEMOUTR_TIMOUTEN (1 << 15)
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/* TIDLE: Idle clock timeout detection */
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#define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12)
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#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12)
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//Not clear yet.
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/* TIMEOUTA[11:0]: Bus Timeout A */
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/* --- I2Cx_ISR values ---------------------------------------------------- */
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/* Bits 31:24 Reserved, must be kept at reset value */
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//Not clear yet.
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/* ADDCODE[6:0]: Address match code (Slave mode) */
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/* DIR: Transfer direction (Slave mode) */
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#define I2C_ISR_DIR_READ (0x1 << 16)
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#define I2C_ISR_DIR_WRITE (0x0 << 16)
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/* BUSY: Bus busy */
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#define I2C_ISR_BUSY (1 << 15)
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/* ALERT: SMBus alert */
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#define I2C_ISR_ALERT (1 << 13)
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/* TIMEOUT: Timeout or tLOW detection flag */
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#define I2C_ISR_TIMEOUT (1 << 12)
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/* PECERR: PEC Error in reception */
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#define I2C_ISR_PECERR (1 << 11)
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/* OVR: Overrun/Underrun (slave mode) */
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#define I2C_ISR_OVR (1 << 10)
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/* ARLO: Arbitration lost */
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#define I2C_ISR_ARLO (1 << 9)
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/* BERR: Bus error */
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#define I2C_ISR_BERR (1 << 8)
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/* TCR: Transfer Complete Reload */
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#define I2C_ISR_TCR (1 << 7)
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/* TC: Transfer Complete (master mode) */
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#define I2C_ISR_TC (1 << 6)
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/* STOPF: Stop detection flag */
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#define I2C_ISR_STOPF (1 << 5)
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/* NACKF: Not Acknowledge received flag */
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#define I2C_ISR_NACKF (1 << 4)
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/* ADDR: Address matched (slave mode) */
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#define I2C_ISR_ADDR (1 << 3)
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/* RXNE: Receive data register not empty (receivers) */
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#define I2C_ISR_RXNE (1 << 2)
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/* TXIS: Transmit interrupt status (transmitters) */
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#define I2C_ISR_TXIS (1 << 1)
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/* TXE: Transmit data register empty (transmitters) */
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#define I2C_ISR_TXE (1 << 0)
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/* --- I2Cx_ICR values ---------------------------------------------------- */
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/* ALERTCF: Alert flag clear */
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#define I2C_ICR_ALERTCF (1 << 13)
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/* TIMOUTCF: Timeout detection flag clear */
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#define I2C_ICR_TIMOUTCF (1 << 12)
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/* PECCF: PEC Error flag clear */
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#define I2C_ICR_PECCF (1 << 11)
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/* OVRCF: Overrun/Underrun flag clear */
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#define I2C_ICR_OVRCF (1 << 10)
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/* ARLOCF: Arbitration Lost flag clear */
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#define I2C_ICR_ARLOCF (1 << 9)
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/* BERRCF: Bus error flag clear */
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#define I2C_ICR_BERRCF (1 << 8)
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/* STOPCF: Stop detection flag clear */
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#define I2C_ICR_STOPCF (1 << 5)
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/* NACKCF: Not Acknowledge flag clear */
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#define I2C_ICR_NACKCF (1 << 4)
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/* ADDRCF: Address Matched flag clear */
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#define I2C_ICR_ADDRCF (1 << 3)
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/* --- I2Cx_PECR values ---------------------------------------------------- */
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/* PEC[7:0] Packet error checking register */
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/* --- I2C constant definitions -------------------------------------------- */
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/****************************************************************************/
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/** @defgroup i2c_rw I2C Read/Write bit
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@ingroup i2c_defines
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@{*/
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#define I2C_WRITE 0
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#define I2C_READ 1
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/**@}*/
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/* --- I2C function prototypes---------------------------------------------- */
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BEGIN_DECLS
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void i2c_reset(uint32_t i2c);
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void i2c_peripheral_enable(uint32_t i2c);
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void i2c_peripheral_disable(uint32_t i2c);
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void i2c_send_start(uint32_t i2c);
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void i2c_send_stop(uint32_t i2c);
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void i2c_clear_stop(uint32_t i2c);
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void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
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void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
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void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
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void i2c_send_data(uint32_t i2c, uint8_t data);
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uint8_t i2c_get_data(uint32_t i2c);
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void i2c_enable_analog_filter(uint32_t i2c);
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void i2c_disable_analog_filter(uint32_t i2c);
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void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting);
|
||||
void i2c_set_prescaler(uint32_t i2c, uint8_t presc);
|
||||
void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time);
|
||||
void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time);
|
||||
void i2c_set_scl_high_period(uint32_t i2c, uint8_t period);
|
||||
void i2c_set_scl_low_period(uint32_t i2c, uint8_t period);
|
||||
void i2c_enable_stretching(uint32_t i2c);
|
||||
void i2c_disable_stretching(uint32_t i2c);
|
||||
void i2c_100khz_i2cclk8mhz(uint32_t i2c);
|
||||
void i2c_set_7bit_addr_mode(uint32_t i2c);
|
||||
void i2c_set_10bit_addr_mode(uint32_t i2c);
|
||||
void i2c_set_7bit_address(uint32_t i2c, uint8_t addr);
|
||||
void i2c_set_10bit_address(uint32_t i2c, uint16_t addr);
|
||||
void i2c_set_write_transfer_dir(uint32_t i2c);
|
||||
void i2c_set_read_transfer_dir(uint32_t i2c);
|
||||
void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes);
|
||||
uint8_t i2c_is_start(uint32_t i2c);
|
||||
void i2c_enable_autoend(uint32_t i2c);
|
||||
void i2c_disable_autoend(uint32_t i2c);
|
||||
uint8_t i2c_nack(uint32_t i2c);
|
||||
uint8_t i2c_busy(uint32_t i2c);
|
||||
uint8_t i2c_transmit_int_status(uint32_t i2c);
|
||||
uint8_t i2c_transfer_complete(uint32_t i2c);
|
||||
uint8_t i2c_received_data(uint32_t i2c);
|
||||
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
|
||||
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
|
||||
void i2c_enable_rxdma(uint32_t i2c);
|
||||
void i2c_disable_rxdma(uint32_t i2c);
|
||||
void i2c_enable_txdma(uint32_t i2c);
|
||||
void i2c_disable_txdma(uint32_t i2c);
|
||||
|
||||
END_DECLS
|
||||
|
||||
/**@}*/
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -34,9 +34,9 @@ CFLAGS = -Os -g \
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
|
||||
OBJS = rcc.o gpio.o adc.o exti2.o
|
||||
OBJS = rcc.o gpio.o adc.o exti2.o i2c.o
|
||||
|
||||
OBJS += gpio_common_all.o gpio_common_f234.o i2c_common_all.o\
|
||||
OBJS += gpio_common_all.o gpio_common_f234.o \
|
||||
dac_common_all.o usart_common_all.o crc_common_all.o\
|
||||
iwdg_common_all.o spi_common_all.o dma_common_f13.o\
|
||||
timer_common_all.o timer_common_f24.o flash_common_f234.o
|
||||
|
||||
@ -29,5 +29,374 @@ LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
#include <libopencm3/stm32/common/i2c_common_all.h>
|
||||
#include <libopencm3/stm32/rcc.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Reset.
|
||||
|
||||
The I2C peripheral and all its associated configuration registers are placed in
|
||||
the reset condition. The reset is effected via the RCC peripheral reset system.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
|
||||
*/
|
||||
|
||||
void i2c_reset(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST);
|
||||
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST);
|
||||
break;
|
||||
case I2C2:
|
||||
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST);
|
||||
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Peripheral Enable.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
|
||||
void i2c_peripheral_enable(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) |= I2C_CR1_PE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Peripheral Disable.
|
||||
|
||||
This must not be reset while in Master mode until a communication has finished.
|
||||
In Slave mode, the peripheral is disabled only after communication has ended.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
|
||||
void i2c_peripheral_disable(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_PE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Send Start Condition.
|
||||
|
||||
If in Master mode this will cause a restart condition to occur at the end of the
|
||||
current transmission. If in Slave mode, this will initiate a start condition
|
||||
when the current bus activity is completed.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
|
||||
void i2c_send_start(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) |= I2C_CR2_START;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Send Stop Condition.
|
||||
|
||||
After the current byte transfer this will initiate a stop condition if in Master
|
||||
mode, or simply release the bus if in Slave mode.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
|
||||
void i2c_send_stop(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) |= I2C_CR2_STOP;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Clear Stop Flag.
|
||||
|
||||
Clear the "Send Stop" flag in the I2C config register
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
void i2c_clear_stop(uint32_t i2c)
|
||||
{
|
||||
I2C_ICR(i2c) |= I2C_ICR_STOPCF;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
|
||||
|
||||
This sets an address for Slave mode operation, in 7 bit form.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
@param[in] slave Unsigned int8. Slave address 0...127.
|
||||
*/
|
||||
|
||||
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
|
||||
{
|
||||
I2C_OAR1(i2c) = (uint16_t)(slave << 1);
|
||||
I2C_OAR1(i2c) &= ~I2C_OAR1_OA1MODE;
|
||||
I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
|
||||
|
||||
This sets an address for Slave mode operation, in 10 bit form.
|
||||
|
||||
@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
@param[in] slave Unsigned int16. Slave address 0...1023.
|
||||
*/
|
||||
|
||||
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
|
||||
{
|
||||
I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_OA1MODE | slave);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Send Data.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
@param[in] data Unsigned int8. Byte to send.
|
||||
*/
|
||||
|
||||
void i2c_send_data(uint32_t i2c, uint8_t data)
|
||||
{
|
||||
I2C_TXDR(i2c) = data;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Get Data.
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
uint8_t i2c_get_data(uint32_t i2c)
|
||||
{
|
||||
return(I2C_RXDR(i2c) & 0xff);
|
||||
}
|
||||
|
||||
void i2c_enable_analog_filter(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF;
|
||||
}
|
||||
|
||||
void i2c_disable_analog_filter(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) |= I2C_CR1_ANFOFF;
|
||||
}
|
||||
|
||||
void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting)
|
||||
{
|
||||
I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting;
|
||||
}
|
||||
|
||||
/* t_presc= (presc+1)*t_i2cclk */
|
||||
void i2c_set_prescaler(uint32_t i2c, uint8_t presc)
|
||||
{
|
||||
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) | (presc << I2C_TIMINGR_PRESC_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time)
|
||||
{
|
||||
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) | (s_time << I2C_TIMINGR_SCLDEL_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time)
|
||||
{
|
||||
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) | (h_time << I2C_TIMINGR_SDADEL_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_set_scl_high_period(uint32_t i2c, uint8_t period)
|
||||
{
|
||||
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) | (period << I2C_TIMINGR_SCLH_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_set_scl_low_period(uint32_t i2c, uint8_t period)
|
||||
{
|
||||
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) | (period << I2C_TIMINGR_SCLL_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_enable_stretching(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH;
|
||||
}
|
||||
|
||||
void i2c_disable_stretching(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH;
|
||||
}
|
||||
|
||||
void i2c_100khz_i2cclk8mhz(uint32_t i2c)
|
||||
{
|
||||
i2c_set_prescaler(i2c, 1);
|
||||
i2c_set_scl_low_period(i2c, 0x13);
|
||||
i2c_set_scl_high_period(i2c, 0xF);
|
||||
i2c_set_data_hold_time(i2c, 0x2);
|
||||
i2c_set_data_setup_time(i2c, 0x4);
|
||||
}
|
||||
|
||||
void i2c_set_7bit_addr_mode(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) &= ~I2C_CR2_ADD10;
|
||||
}
|
||||
|
||||
void i2c_set_10bit_addr_mode(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) |= I2C_CR2_ADD10;
|
||||
}
|
||||
|
||||
void i2c_set_7bit_address(uint32_t i2c, uint8_t addr)
|
||||
{
|
||||
I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) | ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_set_10bit_address(uint32_t i2c, uint16_t addr)
|
||||
{
|
||||
I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) | ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT);
|
||||
}
|
||||
|
||||
void i2c_set_write_transfer_dir(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN;
|
||||
}
|
||||
|
||||
void i2c_set_read_transfer_dir(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) |= I2C_CR2_RD_WRN;
|
||||
}
|
||||
|
||||
void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes)
|
||||
{
|
||||
I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) | (n_bytes << I2C_CR2_NBYTES_SHIFT);
|
||||
}
|
||||
|
||||
uint8_t i2c_is_start(uint32_t i2c)
|
||||
{
|
||||
if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) {
|
||||
return(1);
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_enable_autoend(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) |= I2C_CR2_AUTOEND;
|
||||
}
|
||||
|
||||
void i2c_disable_autoend(uint32_t i2c)
|
||||
{
|
||||
I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND;
|
||||
}
|
||||
|
||||
uint8_t i2c_nack(uint32_t i2c)
|
||||
{
|
||||
if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) {
|
||||
return(1);
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t i2c_busy(uint32_t i2c)
|
||||
{
|
||||
if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) {
|
||||
return(1);
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t i2c_transmit_int_status(uint32_t i2c)
|
||||
{
|
||||
if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) {
|
||||
return(1);
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t i2c_transfer_complete(uint32_t i2c)
|
||||
{
|
||||
if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) {
|
||||
return(1);
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t i2c_received_data(uint32_t i2c)
|
||||
{
|
||||
if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) {
|
||||
return(1);
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Enable Interrupt
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
@param[in] interrupt Unsigned int32. Interrupt to enable.
|
||||
*/
|
||||
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
|
||||
{
|
||||
I2C_CR1(i2c) |= interrupt;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Disable Interrupt
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
@param[in] interrupt Unsigned int32. Interrupt to disable.
|
||||
*/
|
||||
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
|
||||
{
|
||||
I2C_CR1(i2c) &= ~interrupt;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Enable reception DMA
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
void i2c_enable_rxdma(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) |= I2C_CR1_RXDMAEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Disable reception DMA
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
void i2c_disable_rxdma(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Enable transmission DMA
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
void i2c_enable_txdma(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) |= I2C_CR1_TXDMAEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief I2C Disable transmission DMA
|
||||
|
||||
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
|
||||
*/
|
||||
void i2c_disable_txdma(uint32_t i2c)
|
||||
{
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user