stm32f3: rcc: consistent masks for pll multiplier
All other masks consistently used a separate mask/shift define, bring the pll multiplier function in line, and use the same form as other functions.
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@ -105,6 +105,7 @@
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/* PLLMUL: PLL multiplication factor */
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#define RCC_CFGR_PLLMUL_SHIFT 18
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#define RCC_CFGR_PLLMUL_MASK 0xF
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2
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@ -120,7 +121,6 @@
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE
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#define RCC_CFGR_PLLMUL_MASK (0xF << RCC_CFGR_PLLMUL_SHIFT)
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_SHIFT 11
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@ -368,8 +368,11 @@ void rcc_set_hpre(uint32_t hpre)
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void rcc_set_pll_multiplier(uint32_t pll)
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{
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RCC_CFGR = (~RCC_CFGR_PLLMUL_MASK & RCC_CFGR) |
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(pll << RCC_CFGR_PLLMUL_SHIFT);
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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RCC_CFGR = (reg32 | (pll << RCC_CFGR_PLLMUL_SHIFT));
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}
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