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stm32f3: rcc: consistent masks for pll multiplier

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All other masks consistently used a separate mask/shift define, bring the pll
multiplier function in line, and use the same form as other functions.
This commit is contained in:
Karl Palsson 2015-10-22 22:35:48 +00:00
parent 129a874cf8
commit 4d7694b454
2 changed files with 6 additions and 3 deletions
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2
include/libopencm3/stm32/f3/rcc.h
View File

@ -105,6 +105,7 @@
/* PLLMUL: PLL multiplication factor */ /* PLLMUL: PLL multiplication factor */
#define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL_SHIFT 18
#define RCC_CFGR_PLLMUL_MASK 0xF
#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0
#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1
#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2
@ -120,7 +121,6 @@
#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC
#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD
#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE
#define RCC_CFGR_PLLMUL_MASK (0xF << RCC_CFGR_PLLMUL_SHIFT)
/* PPRE2: APB high-speed prescaler (APB2) */ /* PPRE2: APB high-speed prescaler (APB2) */
#define RCC_CFGR_PPRE2_SHIFT 11 #define RCC_CFGR_PPRE2_SHIFT 11

7
lib/stm32/f3/rcc.c
View File

@ -368,8 +368,11 @@ void rcc_set_hpre(uint32_t hpre)
void rcc_set_pll_multiplier(uint32_t pll) void rcc_set_pll_multiplier(uint32_t pll)
{ {
RCC_CFGR = (~RCC_CFGR_PLLMUL_MASK & RCC_CFGR) | uint32_t reg32;
(pll << RCC_CFGR_PLLMUL_SHIFT);
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
RCC_CFGR = (reg32 | (pll << RCC_CFGR_PLLMUL_SHIFT));
} }