lm4f: Appease checkpath.pl and de-typedef enums
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -45,13 +45,13 @@ LGPL License Terms @ref lgpl_license
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*
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*
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* Possible values of the oscillator source.
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* Possible values of the oscillator source.
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*/
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*/
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typedef enum {
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enum osc_src {
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OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
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OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
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OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
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OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
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OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
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OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
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OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
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OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
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OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
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OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
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} osc_src_t;
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};
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/**
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/**
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* \brief PWM clock divisor values
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* \brief PWM clock divisor values
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@ -59,14 +59,14 @@ typedef enum {
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* Possible values of the binary divisor used to predivide the system clock down
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* Possible values of the binary divisor used to predivide the system clock down
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* for use as the timing reference for the PWM module.
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* for use as the timing reference for the PWM module.
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*/
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*/
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typedef enum {
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enum pwm_clkdiv {
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PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
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PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
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PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
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PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
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PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
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PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
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PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
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PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
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PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
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PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
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PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
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PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
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} pwm_clkdiv_t;
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};
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/**
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/**
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* \brief Predefined crystal values
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* \brief Predefined crystal values
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@ -76,7 +76,7 @@ typedef enum {
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* SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
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* SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
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* of 400MHz.
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* of 400MHz.
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*/
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*/
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typedef enum {
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enum xtal_t {
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XTAL_4M = SYSCTL_RCC_XTAL_4M,
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XTAL_4M = SYSCTL_RCC_XTAL_4M,
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XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
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XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
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XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
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XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
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@ -98,14 +98,14 @@ typedef enum {
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XTAL_20M = SYSCTL_RCC_XTAL_20M,
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XTAL_20M = SYSCTL_RCC_XTAL_20M,
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XTAL_24M = SYSCTL_RCC_XTAL_24M,
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XTAL_24M = SYSCTL_RCC_XTAL_24M,
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XTAL_25M = SYSCTL_RCC_XTAL_25M,
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XTAL_25M = SYSCTL_RCC_XTAL_25M,
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} xtal_t;
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};
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/* =============================================================================
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/* =============================================================================
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* Function prototypes
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* Function prototypes
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* ---------------------------------------------------------------------------*/
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* ---------------------------------------------------------------------------*/
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BEGIN_DECLS
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BEGIN_DECLS
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/* Low-level clock API */
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/* Low-level clock API */
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void rcc_configure_xtal(xtal_t xtal);
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void rcc_configure_xtal(enum xtal_t xtal);
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void rcc_disable_main_osc(void);
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void rcc_disable_main_osc(void);
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void rcc_disable_interal_osc(void);
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void rcc_disable_interal_osc(void);
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void rcc_enable_main_osc(void);
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void rcc_enable_main_osc(void);
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@ -113,18 +113,18 @@ void rcc_enable_interal_osc(void);
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void rcc_enable_rcc2(void);
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void rcc_enable_rcc2(void);
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void rcc_pll_off(void);
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void rcc_pll_off(void);
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void rcc_pll_on(void);
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void rcc_pll_on(void);
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void rcc_set_osc_source(osc_src_t src);
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void rcc_set_osc_source(enum osc_src src);
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void rcc_pll_bypass_disable(void);
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void rcc_pll_bypass_disable(void);
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void rcc_pll_bypass_enable(void);
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void rcc_pll_bypass_enable(void);
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void rcc_set_pll_divisor(uint8_t div400);
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void rcc_set_pll_divisor(uint8_t div400);
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void rcc_set_pwm_divisor(pwm_clkdiv_t div);
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void rcc_set_pwm_divisor(enum pwm_clkdiv div);
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void rcc_usb_pll_off(void);
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void rcc_usb_pll_off(void);
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void rcc_usb_pll_on(void);
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void rcc_usb_pll_on(void);
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void rcc_wait_for_pll_ready(void);
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void rcc_wait_for_pll_ready(void);
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/* High-level clock API */
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/* High-level clock API */
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void rcc_change_pll_divisor(uint8_t plldiv400);
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void rcc_change_pll_divisor(uint8_t plldiv400);
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uint32_t rcc_get_system_clock_frequency(void);
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uint32_t rcc_get_system_clock_frequency(void);
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void rcc_sysclk_config(osc_src_t src, xtal_t xtal, uint8_t pll_div400);
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void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400);
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END_DECLS
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END_DECLS
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@ -486,7 +486,7 @@ LGPL License Terms @ref lgpl_license
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* SCC for sleep clock
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* SCC for sleep clock
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* DCC for deep-sleep clock
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* DCC for deep-sleep clock
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*/
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*/
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typedef enum {
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enum lm4f_clken {
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/*
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/*
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* Run clock control
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* Run clock control
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*/
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*/
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@ -725,15 +725,15 @@ typedef enum {
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DCC_WTIMER4,
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DCC_WTIMER4,
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DCC_WTIMER5,
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DCC_WTIMER5,
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} clken_t;
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};
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/* ============================================================================
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/* ============================================================================
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* Function prototypes
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* Function prototypes
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* --------------------------------------------------------------------------*/
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* --------------------------------------------------------------------------*/
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BEGIN_DECLS
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BEGIN_DECLS
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void periph_clock_enable(clken_t periph);
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void periph_clock_enable(enum lm4f_clken periph);
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void periph_clock_disable(clken_t periph);
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void periph_clock_disable(enum lm4f_clken periph);
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END_DECLS
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END_DECLS
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@ -116,7 +116,7 @@ uint32_t lm4f_rcc_sysclk_freq = 16000000;
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*
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*
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* @param[in] xtal predefined crystal type @see xtal_t
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* @param[in] xtal predefined crystal type @see xtal_t
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*/
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*/
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void rcc_configure_xtal(xtal_t xtal)
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void rcc_configure_xtal(enum xtal_t xtal)
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{
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{
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uint32_t reg32;
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uint32_t reg32;
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@ -213,7 +213,7 @@ void rcc_pll_on(void)
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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* function.
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*/
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*/
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void rcc_set_osc_source(osc_src_t src)
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void rcc_set_osc_source(enum osc_src src)
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{
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{
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uint32_t reg32;
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uint32_t reg32;
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@ -291,7 +291,7 @@ void rcc_set_pll_divisor(uint8_t div400)
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*
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*
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* @param[in] div clock divisor to use @see pwm_clkdiv_t
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* @param[in] div clock divisor to use @see pwm_clkdiv_t
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*/
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*/
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void rcc_set_pwm_divisor(pwm_clkdiv_t div)
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void rcc_set_pwm_divisor(enum pwm_clkdiv div)
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{
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{
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uint32_t reg32;
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uint32_t reg32;
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@ -385,8 +385,8 @@ uint32_t rcc_get_system_clock_frequency(void)
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return lm4f_rcc_sysclk_freq;
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return lm4f_rcc_sysclk_freq;
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}
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}
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/* Get the clock frequency corresponging to a given XTAL value */
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/* Get the clock frequency corresponding to a given XTAL value */
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static uint32_t xtal_to_freq(xtal_t xtal)
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static uint32_t xtal_to_freq(enum xtal_t xtal)
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{
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{
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const uint32_t freqs[] = {
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const uint32_t freqs[] = {
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4000000, /* XTAL_4M */
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4000000, /* XTAL_4M */
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@ -440,7 +440,7 @@ static uint32_t xtal_to_freq(xtal_t xtal)
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*
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*
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* @return System clock frequency in Hz
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* @return System clock frequency in Hz
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*/
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*/
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void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400)
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void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400)
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{
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{
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/*
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/*
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* We could be using the PLL at this point, or we could be running of a
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* We could be using the PLL at this point, or we could be running of a
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@ -449,7 +449,7 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400)
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rcc_pll_bypass_enable();
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rcc_pll_bypass_enable();
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/* Enable the main oscillator, if needed */
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/* Enable the main oscillator, if needed */
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if (osc_src == OSCSRC_MOSC) {
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if (src == OSCSRC_MOSC) {
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rcc_enable_main_osc();
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rcc_enable_main_osc();
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}
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}
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@ -459,7 +459,7 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400)
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/* Set XTAL value to 16MHz */
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/* Set XTAL value to 16MHz */
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rcc_configure_xtal(xtal);
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rcc_configure_xtal(xtal);
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/* Set the oscillator source */
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/* Set the oscillator source */
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rcc_set_osc_source(osc_src);
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rcc_set_osc_source(src);
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if (pll_div400) {
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if (pll_div400) {
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/* Enable the PLL */
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/* Enable the PLL */
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rcc_pll_on();
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rcc_pll_on();
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@ -467,7 +467,7 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400)
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rcc_change_pll_divisor(pll_div400);
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rcc_change_pll_divisor(pll_div400);
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} else {
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} else {
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/* We are running off a raw clock */
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/* We are running off a raw clock */
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switch (osc_src) {
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switch (src) {
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case OSCSRC_PIOSC:
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case OSCSRC_PIOSC:
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lm4f_rcc_sysclk_freq = 16000000;
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lm4f_rcc_sysclk_freq = 16000000;
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break;
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break;
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@ -22,9 +22,9 @@
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/**
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/**
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* \brief Enable the clock source for the peripheral
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* \brief Enable the clock source for the peripheral
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*
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*
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* @param[in] periph peripheral and clock type to enable @see clken_t
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* @param[in] periph peripheral and clock type to enable @see lm4f_clken
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*/
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*/
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void periph_clock_enable(clken_t periph)
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void periph_clock_enable(enum lm4f_clken periph)
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{
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{
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MMIO32(SYSCTL_BASE + (periph >> 5)) |= 1 << (periph & 0x1f);
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MMIO32(SYSCTL_BASE + (periph >> 5)) |= 1 << (periph & 0x1f);
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}
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}
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@ -32,9 +32,9 @@ void periph_clock_enable(clken_t periph)
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/**
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/**
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* \brief Disable the clock source for the peripheral
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* \brief Disable the clock source for the peripheral
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*
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*
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* @param[in] periph peripheral and clock type to enable @see clken_t
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* @param[in] periph peripheral and clock type to enable @see lm4f_clken
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*/
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*/
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void periph_clock_disable(clken_t periph)
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void periph_clock_disable(enum lm4f_clken periph)
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{
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{
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MMIO32(SYSCTL_BASE + (periph >> 5)) &= ~(1 << (periph & 0x1f));
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MMIO32(SYSCTL_BASE + (periph >> 5)) &= ~(1 << (periph & 0x1f));
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}
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}
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