BREAKING: stm32f3:rcc: use more common MUL names
Make the defines as they are on other families, try and make more defines the same, not arbitrarily different.
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@ -106,21 +106,21 @@
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/* PLLMUL: PLL multiplication factor */
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/* PLLMUL: PLL multiplication factor */
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#define RCC_CFGR_PLLMUL_SHIFT 18
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#define RCC_CFGR_PLLMUL_SHIFT 18
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#define RCC_CFGR_PLLMUL_MASK 0xF
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#define RCC_CFGR_PLLMUL_MASK 0xF
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0
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#define RCC_CFGR_PLLMUL_MUL2 0x0
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1
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#define RCC_CFGR_PLLMUL_MUL3 0x1
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2
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#define RCC_CFGR_PLLMUL_MUL4 0x2
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X5 0x3
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#define RCC_CFGR_PLLMUL_MUL5 0x3
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X6 0x4
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#define RCC_CFGR_PLLMUL_MUL6 0x4
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X7 0x5
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#define RCC_CFGR_PLLMUL_MUL7 0x5
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X8 0x6
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#define RCC_CFGR_PLLMUL_MUL8 0x6
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X9 0x7
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#define RCC_CFGR_PLLMUL_MUL9 0x7
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X10 0x8
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#define RCC_CFGR_PLLMUL_MUL10 0x8
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X11 0x9
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#define RCC_CFGR_PLLMUL_MUL11 0x9
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X12 0xA
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#define RCC_CFGR_PLLMUL_MUL12 0xA
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X13 0xB
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#define RCC_CFGR_PLLMUL_MUL13 0xB
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC
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#define RCC_CFGR_PLLMUL_MUL14 0xC
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD
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#define RCC_CFGR_PLLMUL_MUL15 0xD
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE
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#define RCC_CFGR_PLLMUL_MUL16 0xE
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/* PPRE2: APB high-speed prescaler (APB2) */
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_SHIFT 11
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#define RCC_CFGR_PPRE2_SHIFT 11
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@ -46,7 +46,7 @@ uint32_t rcc_apb2_frequency = 8000000;
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const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
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const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
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{ /* 44MHz */
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{ /* 44MHz */
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.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X11,
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.pll = RCC_CFGR_PLLMUL_MUL11,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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@ -57,7 +57,7 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
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.apb2_frequency = 44000000,
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.apb2_frequency = 44000000,
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},
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},
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{ /* 48MHz */
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{ /* 48MHz */
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.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X12,
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.pll = RCC_CFGR_PLLMUL_MUL12,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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@ -68,7 +68,7 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
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.apb2_frequency = 48000000,
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.apb2_frequency = 48000000,
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},
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},
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{ /* 64MHz */
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{ /* 64MHz */
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.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X16,
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.pll = RCC_CFGR_PLLMUL_MUL16,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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