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[Style] checked and corrected

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BuFran 2013-07-08 17:40:41 +02:00 committed by Piotr Esden-Tempski
parent c6f861139d
commit 65eaad938f
6 changed files with 75 additions and 71 deletions
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2
include/libopencm3/lpc43xx/gpdma.h
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@ -489,7 +489,7 @@
cacheable */
#define GPDMA_CxCONTROL_PROT3_SHIFT (30)
#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT)
#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT)
#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT)
/* I: Terminal count interrupt enable bit */
#define GPDMA_CxCONTROL_I_SHIFT (31)

2
include/libopencm3/lpc43xx/uart.h
View File

@ -429,7 +429,7 @@ void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num);
uint8_t uart_read(uart_num_t uart_num);
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
uart_error_t *error);
void uart_write(uart_num_t uart_num, uint8_t data);

8
lib/lpc43xx/ipc.c
View File

@ -30,8 +30,7 @@ void ipc_halt_m0(void)
rst_active_status1 = RESET_ACTIVE_STATUS1;
/* If the M0 has reset not asserted, halt it... */
while( (rst_active_status1 & RESET_CTRL1_M0APP_RST) )
{
while (rst_active_status1 & RESET_CTRL1_M0APP_RST) {
RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST);
rst_active_status1 = RESET_ACTIVE_STATUS1;
}
@ -51,9 +50,8 @@ void ipc_start_m0(uint32_t cm0_baseaddr)
/* If the M0 is being held in reset, release it */
/* 1 = no reset, 0 = reset */
while( !(rst_active_status1 & RESET_CTRL1_M0APP_RST) )
{
RESET_CTRL1 = ((~rst_active_status1) & (~RESET_CTRL1_M0APP_RST));
while (!(rst_active_status1 & RESET_CTRL1_M0APP_RST)) {
RESET_CTRL1 = ((~rst_active_status1) & ~RESET_CTRL1_M0APP_RST);
rst_active_status1 = RESET_ACTIVE_STATUS1;
}
}

4
lib/lpc43xx/ssp.c
View File

@ -128,9 +128,9 @@ uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data)
* example...
*/
ssp_wait_until_not_busy(ssp_num);
/* Wait Until Data Received (Rx FIFO not Empty) */
while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
while ((SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
return SSP_DR(ssp_port);
}

22
lib/lpc43xx/timer.c
View File

@ -24,47 +24,49 @@
void timer_reset(uint32_t timer_peripheral)
{
TIMER_TCR(timer_peripheral) |= TIMER_TCR_CRST;
TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CRST;
TIMER_TCR(timer_peripheral) |= TIMER_TCR_CRST;
TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CRST;
}
void timer_enable_counter(uint32_t timer_peripheral)
{
TIMER_TCR(timer_peripheral) |= TIMER_TCR_CEN;
TIMER_TCR(timer_peripheral) |= TIMER_TCR_CEN;
}
void timer_disable_counter(uint32_t timer_peripheral)
{
TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CEN;
TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CEN;
}
void timer_set_counter(uint32_t timer_peripheral, uint32_t count)
{
TIMER_TC(timer_peripheral) = count;
TIMER_TC(timer_peripheral) = count;
}
uint32_t timer_get_counter(uint32_t timer_peripheral)
{
return TIMER_TC(timer_peripheral);
return TIMER_TC(timer_peripheral);
}
uint32_t timer_get_prescaler(uint32_t timer_peripheral)
{
return TIMER_PR(timer_peripheral);
return TIMER_PR(timer_peripheral);
}
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler)
{
TIMER_PR(timer_peripheral) = prescaler;
TIMER_PR(timer_peripheral) = prescaler;
}
void timer_set_mode(uint32_t timer_peripheral, uint32_t mode)
{
TIMER_CTCR(timer_peripheral) = (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK) | mode;
TIMER_CTCR(timer_peripheral) = mode |
(TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK);
}
void timer_set_count_input(uint32_t timer_peripheral, uint32_t input)
{
TIMER_CTCR(timer_peripheral) = (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK) | input;
TIMER_CTCR(timer_peripheral) = input |
(TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK);
}

108
lib/lpc43xx/uart.c
View File

@ -36,70 +36,71 @@
#define UART_SRC_IDIVE 0x10
#define UART_CGU_AUTOBLOCK_CLOCK_BIT 11
#define UART_CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
/* clock source selection (5 bits) */
#define UART_CGU_BASE_CLK_SEL_SHIFT 24
uint32_t dummy_read;
/*
* UART Init function
*/
void uart_init(uart_num_t uart_num,
uart_databit_t data_nb_bits,
uart_stopbit_t data_nb_stop,
uart_parity_t data_parity,
uint16_t uart_divisor,
uint8_t uart_divaddval,
uint8_t uart_mulval)
void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
uart_stopbit_t data_nb_stop, uart_parity_t data_parity,
uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval)
{
uint32_t lcr_config;
uint32_t uart_port;
uart_port = uart_num;
switch(uart_num)
{
case UART0_NUM:
/* use PLL1 as clock source for UART0 */
CGU_BASE_UART0_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
switch (uart_num) {
case UART0_NUM:
/* use PLL1 as clock source for UART0 */
CGU_BASE_UART0_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
case UART1_NUM:
/* use PLL1 as clock source for UART1 */
CGU_BASE_UART1_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
case UART1_NUM:
/* use PLL1 as clock source for UART1 */
CGU_BASE_UART1_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
case UART2_NUM:
/* use PLL1 as clock source for UART2 */
CGU_BASE_UART2_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
case UART2_NUM:
/* use PLL1 as clock source for UART2 */
CGU_BASE_UART2_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
case UART3_NUM:
/* use PLL1 as clock source for UART3 */
CGU_BASE_UART3_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
break;
case UART3_NUM:
/* use PLL1 as clock source for UART3 */
CGU_BASE_UART3_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
default:
return; /* error */
default:
return; /* error */
}
/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared) */
UART_FCR(uart_port) = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared)*/
UART_FCR(uart_port) = (UART_FCR_FIFO_EN | UART_FCR_RX_RS |
UART_FCR_TX_RS);
/* Disable FIFO */
UART_FCR(uart_port) = 0;
// Dummy read (to clear existing data)
while (UART_LSR(uart_port) & UART_LSR_RDR ) {
/* Dummy read (to clear existing data) */
while (UART_LSR(uart_port) & UART_LSR_RDR) {
dummy_read = UART_RBR(uart_port);
}
/* Wait end of TX & disable TX */
UART_TER(uart_port) = UART_TER_TXEN;
UART_TER(uart_port) = UART_TER_TXEN;
/* Wait for current transmit complete */
while (!(UART_LSR(uart_port) & UART_LSR_THRE));
/* Wait for current transmit complete */
while (!(UART_LSR(uart_port) & UART_LSR_THRE));
/* Disable Tx */
UART_TER(uart_port) = 0;
/* Disable Tx */
UART_TER(uart_port) = 0;
/* Disable interrupt */
UART_IER(uart_port) = 0;
@ -114,12 +115,13 @@ void uart_init(uart_num_t uart_num,
dummy_read = UART_LSR(uart_port);
/*
Table 835. USART Fractional Divider Register:
UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 <= MULVAL <= 15
2. 0 <= DIVADDVAL <= 14
3. DIVADDVAL < MULVAL
Table 835. USART Fractional Divider Register:
UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
The value of MULVAL and DIVADDVAL should comply to the following
conditions:
1. 1 <= MULVAL <= 15
2. 0 <= DIVADDVAL <= 14
3. DIVADDVAL < MULVAL
*/
/* Set DLAB Bit */
@ -128,10 +130,12 @@ void uart_init(uart_num_t uart_num,
UART_DLL(uart_port) = UART_LOAD_DLL(uart_divisor);
/* Clear DLAB Bit */
UART_LCR(uart_port) &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
UART_FDR(uart_port) = (UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval)) & UART_FDR_BITMASK;
UART_FDR(uart_port) = UART_FDR_BITMASK &
(UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval));
/* Read LCR config & Force Enable of Divisor Latches Access */
lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) &
UART_LCR_BITMASK;
lcr_config |= data_nb_bits; /* Set Nb Data Bits */
lcr_config |= data_nb_stop; /* Set Nb Stop Bits */
lcr_config |= data_parity; /* Set Data Parity */
@ -140,7 +144,7 @@ void uart_init(uart_num_t uart_num,
UART_LCR(uart_port) = (lcr_config & UART_LCR_BITMASK);
/* Enable TX */
UART_TER(uart_port) = UART_TER_TXEN;
UART_TER(uart_port) = UART_TER_TXEN;
}
/*
@ -193,7 +197,8 @@ uint8_t uart_read(uart_num_t uart_num)
/*
* This Function Wait until Data RX Ready, and return Data Read from UART.
*/
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t* error)
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
uart_error_t *error)
{
uint32_t uart_port;
uint8_t uart_val;
@ -203,11 +208,10 @@ uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, ua
/* Wait Until Data Received (Rx Data Not Ready) */
counter = 0;
while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0)
{
if (rx_timeout_nb_cycles>0) {
while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0) {
if (rx_timeout_nb_cycles > 0) {
counter++;
if (counter>=rx_timeout_nb_cycles) {
if (counter >= rx_timeout_nb_cycles) {
*error = UART_TIMEOUT_ERROR;
return 0;
}
@ -222,7 +226,7 @@ uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, ua
return uart_val;
}
/* This Function Wait Data TX Ready, and Write Data to UART
/* This Function Wait Data TX Ready, and Write Data to UART
if rx_timeout_nb_cycles = 0 Infinite wait
*/
void uart_write(uart_num_t uart_num, uint8_t data)