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[Style] checked and corrected

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BuFran 2013-07-08 17:40:41 +02:00 committed by Piotr Esden-Tempski
parent c6f861139d
commit 65eaad938f
6 changed files with 75 additions and 71 deletions
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8
lib/lpc43xx/ipc.c
View File

@ -30,8 +30,7 @@ void ipc_halt_m0(void)
rst_active_status1 = RESET_ACTIVE_STATUS1;
/* If the M0 has reset not asserted, halt it... */
while( (rst_active_status1 & RESET_CTRL1_M0APP_RST) )
{
while (rst_active_status1 & RESET_CTRL1_M0APP_RST) {
RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST);
rst_active_status1 = RESET_ACTIVE_STATUS1;
}
@ -51,9 +50,8 @@ void ipc_start_m0(uint32_t cm0_baseaddr)
/* If the M0 is being held in reset, release it */
/* 1 = no reset, 0 = reset */
while( !(rst_active_status1 & RESET_CTRL1_M0APP_RST) )
{
RESET_CTRL1 = ((~rst_active_status1) & (~RESET_CTRL1_M0APP_RST));
while (!(rst_active_status1 & RESET_CTRL1_M0APP_RST)) {
RESET_CTRL1 = ((~rst_active_status1) & ~RESET_CTRL1_M0APP_RST);
rst_active_status1 = RESET_ACTIVE_STATUS1;
}
}

6
lib/lpc43xx/timer.c
View File

@ -60,11 +60,13 @@ void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler)
void timer_set_mode(uint32_t timer_peripheral, uint32_t mode)
{
TIMER_CTCR(timer_peripheral) = (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK) | mode;
TIMER_CTCR(timer_peripheral) = mode |
(TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK);
}
void timer_set_count_input(uint32_t timer_peripheral, uint32_t input)
{
TIMER_CTCR(timer_peripheral) = (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK) | input;
TIMER_CTCR(timer_peripheral) = input |
(TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK);
}

48
lib/lpc43xx/uart.c
View File

@ -36,46 +36,46 @@
#define UART_SRC_IDIVE 0x10
#define UART_CGU_AUTOBLOCK_CLOCK_BIT 11
#define UART_CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
/* clock source selection (5 bits) */
#define UART_CGU_BASE_CLK_SEL_SHIFT 24
uint32_t dummy_read;
/*
* UART Init function
*/
void uart_init(uart_num_t uart_num,
uart_databit_t data_nb_bits,
uart_stopbit_t data_nb_stop,
uart_parity_t data_parity,
uint16_t uart_divisor,
uint8_t uart_divaddval,
uint8_t uart_mulval)
void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
uart_stopbit_t data_nb_stop, uart_parity_t data_parity,
uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval)
{
uint32_t lcr_config;
uint32_t uart_port;
uart_port = uart_num;
switch(uart_num)
{
switch (uart_num) {
case UART0_NUM:
/* use PLL1 as clock source for UART0 */
CGU_BASE_UART0_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
CGU_BASE_UART0_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
case UART1_NUM:
/* use PLL1 as clock source for UART1 */
CGU_BASE_UART1_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
CGU_BASE_UART1_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
case UART2_NUM:
/* use PLL1 as clock source for UART2 */
CGU_BASE_UART2_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
CGU_BASE_UART2_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
case UART3_NUM:
/* use PLL1 as clock source for UART3 */
CGU_BASE_UART3_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
CGU_BASE_UART3_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
break;
default:
@ -83,11 +83,12 @@ void uart_init(uart_num_t uart_num,
}
/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared)*/
UART_FCR(uart_port) = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
UART_FCR(uart_port) = (UART_FCR_FIFO_EN | UART_FCR_RX_RS |
UART_FCR_TX_RS);
/* Disable FIFO */
UART_FCR(uart_port) = 0;
// Dummy read (to clear existing data)
/* Dummy read (to clear existing data) */
while (UART_LSR(uart_port) & UART_LSR_RDR) {
dummy_read = UART_RBR(uart_port);
}
@ -116,7 +117,8 @@ void uart_init(uart_num_t uart_num,
/*
Table 835. USART Fractional Divider Register:
UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of MULVAL and DIVADDVAL should comply to the following
conditions:
1. 1 <= MULVAL <= 15
2. 0 <= DIVADDVAL <= 14
3. DIVADDVAL < MULVAL
@ -128,10 +130,12 @@ void uart_init(uart_num_t uart_num,
UART_DLL(uart_port) = UART_LOAD_DLL(uart_divisor);
/* Clear DLAB Bit */
UART_LCR(uart_port) &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
UART_FDR(uart_port) = (UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval)) & UART_FDR_BITMASK;
UART_FDR(uart_port) = UART_FDR_BITMASK &
(UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval));
/* Read LCR config & Force Enable of Divisor Latches Access */
lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) &
UART_LCR_BITMASK;
lcr_config |= data_nb_bits; /* Set Nb Data Bits */
lcr_config |= data_nb_stop; /* Set Nb Stop Bits */
lcr_config |= data_parity; /* Set Data Parity */
@ -193,7 +197,8 @@ uint8_t uart_read(uart_num_t uart_num)
/*
* This Function Wait until Data RX Ready, and return Data Read from UART.
*/
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t* error)
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
uart_error_t *error)
{
uint32_t uart_port;
uint8_t uart_val;
@ -203,8 +208,7 @@ uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, ua
/* Wait Until Data Received (Rx Data Not Ready) */
counter = 0;
while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0)
{
while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0) {
if (rx_timeout_nb_cycles > 0) {
counter++;
if (counter >= rx_timeout_nb_cycles) {