Merge commit 'eb46994bc95ba308f8eb96d42366abbdae7c5ab7' into sam-update

.travis.yml

@@ -1,10 +1,11 @@
+dist: trusty
 sudo: required
 
 before_install:
   - sudo add-apt-repository -y ppa:team-gcc-arm-embedded/ppa
   - sudo apt-get update -qq
   - sudo apt-get install -y build-essential libftdi-dev gcc-arm-embedded
-  - sudo pip install intelhex
+  - pip install --user intelhex
 
 install: true
 

scripts/gdb.py

@@ -291,7 +291,7 @@ class Target:
 
 	def flash_write_prepare(self, address, data):
 		for m in self.mem:
-			if (address >= m.offset) and (address + len(data) < m.offset + m.length):
+			if (address >= m.offset) and (address + len(data) <= m.offset + m.length):
 				m.prog(address, data)
 
 	def flash_commit(self, progress_cb=None):

scripts/stm32_mem.py

@@ -39,6 +39,16 @@ def stm32_erase(dev, addr):
 		if status.bState == dfu.STATE_DFU_DOWNLOAD_IDLE:
 			break
 
+def stm32_set_address(dev, addr):
+	set_address_cmd = struct.pack("<BL", CMD_SETADDRESSPOINTER, addr)
+	dev.download(0, set_address_cmd)
+	while True:
+		status = dev.get_status()
+		if status.bState == dfu.STATE_DFU_DOWNLOAD_BUSY:
+			sleep(status.bwPollTimeout / 1000.0)
+		if status.bState == dfu.STATE_DFU_DOWNLOAD_IDLE:
+			break
+
 def stm32_write(dev, data):
 	dev.download(2, data)
 	while True:
@@ -120,6 +130,11 @@ if __name__ == "__main__":
                 except:
 			print "\nErase Timed out\n"
 			break
+		try:
+			stm32_set_address(dfudev, addr)
+		except:
+			print "\nSet Address Timed out\n"
+			break
 		stm32_write(dfudev, bin[:1024])
 
 		bin = bin[1024:]

src/platforms/native/platform.c

@@ -161,7 +161,8 @@ void platform_init(void)
 				GPIO_CNF_INPUT_PULL_UPDOWN, GPIO0);
 	}
 	/* Relocate interrupt vector table here */
-	SCB_VTOR = 0x2000;
+	extern int vector_table;
+	SCB_VTOR = (uint32_t)&vector_table;
 
 	platform_timing_init();
 	cdcacm_init();

src/platforms/stlink/platform.c

@@ -101,7 +101,9 @@ void platform_init(void)
 	gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_2_MHZ,
 	              GPIO_CNF_OUTPUT_PUSHPULL, led_idle_run);
 
-	SCB_VTOR = 0x2000; /* Relocate interrupt vector table here */
+	/* Relocate interrupt vector table here */
+	extern int vector_table;
+	SCB_VTOR = (uint32_t)&vector_table;
 
 	platform_timing_init();
 	cdcacm_init();

src/platforms/swlink/platform.c

@@ -77,7 +77,9 @@ void platform_init(void)
 	data |=  AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1;
 	AFIO_MAPR = data;
 
-	SCB_VTOR = 0x2000;	// Relocate interrupt vector table here
+	/* Relocate interrupt vector table here */
+	extern int vector_table;
+	SCB_VTOR = (uint32_t)&vector_table;
 
 	platform_timing_init();
 	cdcacm_init();

src/target/lmi.c

@@ -89,6 +89,13 @@ bool lmi_probe(target *t)
 		 * only use the AIRCR SYSRESETREQ. */
 		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
 		return true;
+
+	case 0x1022:    /* TM4C1230C3PM */
+		t->driver = lmi_driver_str;
+		target_add_ram(t, 0x20000000, 0x6000);
+		lmi_add_flash(t, 0x10000);
+		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
+		return true;
 	}
 	return false;
 }

src/target/lpc11xx.c

@@ -89,6 +89,13 @@ lpc11xx_probe(target *t)
 		target_add_ram(t, 0x10000000, 0x2000);
 		lpc11xx_add_flash(t, 0x00000000, 0x20000, 0x1000);
 		return true;
+
+	case 0x0A24902B:
+	case 0x1A24902B:
+		t->driver = "LPC1112";
+		target_add_ram(t, 0x10000000, 0x1000);
+		lpc11xx_add_flash(t, 0x00000000, 0x10000, 0x1000);
+		return true;
 	}
 
 	idcode = target_mem_read32(t, LPC8XX_DEVICE_ID);

src/target/nrf51.c

@@ -112,6 +112,7 @@ bool nrf51_probe(target *t)
 	case 0x0020: /* nRF51822 (rev 1) CEAA BA */
 	case 0x0024: /* nRF51422 (rev 1) QFAA C0 */
 	case 0x002A: /* nRF51822 (rev 2) QFAA FA0 */
+	case 0x004A: /* nRF51822 (rev 3) QFAA G1 */ 			
 	case 0x002D: /* nRF51422 (rev 2) QFAA DAA */
 	case 0x002E: /* nRF51422 (rev 2) QFAA E0 */
 	case 0x002F: /* nRF51822 (rev 1) CEAA B0 */
@@ -128,6 +129,7 @@ bool nrf51_probe(target *t)
 	case 0x0079: /* nRF51822 (rev 3) CEAA E0 */
 	case 0x007A: /* nRF51422 (rev 3) CEAA C0 */
 	case 0x008F: /* nRF51822 (rev 3) QFAA H1 See https://devzone.nordicsemi.com/question/97769/can-someone-conform-the-config-id-code-for-the-nrf51822qfaah1/ */
+	case 0x00D1: /* nRF51822 (rev 3) QFAA H2 */		
 		t->driver = "Nordic nRF51";
 		target_add_ram(t, 0x20000000, 0x4000);
 		nrf51_add_flash(t, 0x00000000, 0x40000, NRF51_PAGE_SIZE);
@@ -169,6 +171,13 @@ bool nrf51_probe(target *t)
 		nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
 		target_add_commands(t, nrf51_cmd_list, "nRF52");
 		return true;
+	case 0x00EB: /* nRF52840 Preview QIAA AA0 */
+		t->driver = "Nordic nRF52";
+		target_add_ram(t, 0x20000000, 256*1024);
+		nrf51_add_flash(t, 0x00000000, 1024*1024, NRF52_PAGE_SIZE);
+		nrf51_add_flash(t, NRF51_UICR, 0x100, 0x100);
+		target_add_commands(t, nrf51_cmd_list, "nRF52");
+		return true;
 	}
 
 	return false;

src/target/stm32f1.c

@@ -25,6 +25,11 @@
  * ST doc - RM0008
  *   Reference manual - STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
  *   and STM32F107xx advanced ARM-based 32-bit MCUs
+ * ST doc - RM0091
+ *   Reference manual - STM32F0x1/STM32F0x2/STM32F0x8
+ *   advanced ARM®-based 32-bit MCUs
+ * ST doc - RM0360
+ *   Reference manual - STM32F030x4/x6/x8/xC and STM32F070x6/xB
  * ST doc - PM0075
  *   Programming manual - STM32F10xxx Flash memory microcontrollers
  */
@@ -145,21 +150,21 @@ bool stm32f1_probe(target *t)
 
 	t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
 	switch(t->idcode) {
-	case 0x444:  /* STM32F03 RM0091 Rev.7 */
+	case 0x444:  /* STM32F03 RM0091 Rev.7, STM32F030x[4|6] RM0360 Rev. 4*/
 		t->driver = "STM32F03";
 		break;
-	case 0x445:  /* STM32F04 RM0091 Rev.7 */
+	case 0x445:  /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
-		t->driver = "STM32F04";
+		t->driver = "STM32F04/F070x6";
 		break;
-	case 0x440:  /* STM32F05 RM0091 Rev.7 */
+	case 0x440:  /* STM32F05 RM0091 Rev.7, STM32F030x8 RM0360 Rev. 4*/
-		t->driver = "STM32F05";
+		t->driver = "STM32F05/F030x8";
 		break;
-	case 0x448:  /* STM32F07 RM0091 Rev.7 */
+	case 0x448:  /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
 		t->driver = "STM32F07";
 		block_size = 0x800;
 		break;
-	case 0x442:  /* STM32F09 RM0091 Rev.7 */
+	case 0x442:  /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
-		t->driver = "STM32F09";
+		t->driver = "STM32F09/F030xC";
 		block_size = 0x800;
 		break;
 	default:     /* NONE */

src/target/stm32f4.c

@@ -37,10 +37,12 @@
 
 static bool stm32f4_cmd_erase_mass(target *t);
 static bool stm32f4_cmd_option(target *t, int argc, char *argv[]);
+static bool stm32f4_cmd_psize(target *t, int argc, char *argv[]);
 
 const struct command_s stm32f4_cmd_list[] = {
 	{"erase_mass", (cmd_handler)stm32f4_cmd_erase_mass, "Erase entire flash memory"},
 	{"option", (cmd_handler)stm32f4_cmd_option, "Manipulate option bytes"},
+	{"psize", (cmd_handler)stm32f4_cmd_psize, "Configure flash write parallelism: (x8|x32)"},
 	{NULL, NULL, NULL}
 };
 
@@ -122,6 +124,7 @@ static const uint16_t stm32f4_flash_write_x8_stub[] = {
 struct stm32f4_flash {
 	struct target_flash f;
 	uint8_t base_sector;
+	uint8_t psize;
 };
 
 enum ID_STM32F47 {
@@ -155,6 +158,7 @@ static void stm32f4_add_flash(target *t,
 	f->align = 4;
 	f->erased = 0xff;
 	sf->base_sector = base_sector;
+	sf->psize = 32;
 	target_add_flash(t, f);
 }
 
@@ -180,6 +184,7 @@ bool stm32f4_probe(target *t)
 
 	switch(idcode) {
 	case ID_STM32F42X: /* 427/437 */
+	case ID_STM32F46X: /* 469/479 */
 		/* Second bank for 2M parts. */
 		stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12);
 		stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16);
@@ -223,7 +228,7 @@ bool stm32f4_probe(target *t)
 		stm32f4_add_flash(t, 0x0200000, 0x20000, 0x8000, 0);
 		stm32f4_add_flash(t, 0x0220000, 0x20000, 0x20000, 4);
 		stm32f4_add_flash(t, 0x0240000, 0xC0000, 0x40000, 5);
-		target_add_commands(t, stm32f4_cmd_list, "STM32F4x");
+		target_add_commands(t, stm32f4_cmd_list, "STM32F74x");
 		break;
 	case ID_STM32F76X: /* F76x F77x RM0410 */
 		t->driver = stm32f7_driver_str;
@@ -246,7 +251,7 @@ bool stm32f4_probe(target *t)
 		stm32f4_add_flash(t, 0x8000000, 0x010000, 0x4000,  0);
 		stm32f4_add_flash(t, 0x8010000, 0x010000, 0x10000, 4);
 		stm32f4_add_flash(t, 0x8020000, 0x060000, 0x20000, 3);
-		target_add_commands(t, stm32f4_cmd_list, "STM32F76x");
+		target_add_commands(t, stm32f4_cmd_list, "STM32F72x");
 		break;
 	default:
 		return false;
@@ -308,6 +313,10 @@ static int stm32f4_flash_write(struct target_flash *f,
 	}
 
 	/* Write buffer to target ram call stub */
+	if (((struct stm32f4_flash *)f)->psize == 32)
+		target_mem_write(f->t, SRAM_BASE, stm32f4_flash_write_x32_stub,
+		                 sizeof(stm32f4_flash_write_x32_stub));
+	else
 		target_mem_write(f->t, SRAM_BASE, stm32f4_flash_write_x8_stub,
 		                 sizeof(stm32f4_flash_write_x8_stub));
 	target_mem_write(f->t, STUB_BUFFER_BASE, src, len);
@@ -540,3 +549,33 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[])
 	tc_printf(t, "\n");
 	return true;
 }
+
+static bool stm32f4_cmd_psize(target *t, int argc, char *argv[])
+{
+	if (argc == 1) {
+		uint8_t psize = 8;
+		for (struct target_flash *f = t->flash; f; f = f->next) {
+			if (f->write == stm32f4_flash_write) {
+				psize = ((struct stm32f4_flash *)f)->psize;
+			}
+		}
+		tc_printf(t, "Flash write parallelism: %s\n",
+		          psize == 32 ? "x32" : "x8");
+	} else {
+		uint8_t psize;
+		if (!strcmp(argv[1], "x8")) {
+			psize = 8;
+		} else if (!strcmp(argv[1], "x32")) {
+			psize = 32;
+		} else {
+			tc_printf(t, "usage: monitor psize (x8|x32)\n");
+			return false;
+		}
+		for (struct target_flash *f = t->flash; f; f = f->next) {
+			if (f->write == stm32f4_flash_write) {
+				((struct stm32f4_flash *)f)->psize = psize;
+			}
+		}
+	}
+	return true;
+}