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stm32g0: flash: update registers documentation

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This commit is contained in:
Guillaume Revaillot 2020-04-05 15:52:38 +02:00 committed by Karl Palsson
parent d696e2c264
commit 7cb7d51273
1 changed files with 96 additions and 18 deletions
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114
include/libopencm3/stm32/g0/flash.h
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@ -49,12 +49,19 @@
#define FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) #define FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)
/**@}*/ /**@}*/
/* --- FLASH_ACR values ----------------------------------------------------- */
/** @defgroup flash_acr ACR Access control register
@{*/
/** FLASH_ACR_DBG_SWEN Debug access software enable **/
#define FLASH_ACR_DBG_SWEN (1 << 18) #define FLASH_ACR_DBG_SWEN (1 << 18)
#define FLASH_ACR_EMPTY (1 << 16) /** FLASH_ACR_EMPTY Flash User area empty **/
#define FLASH_ACR_ICRST (1 << 11) #define FLASH_ACR_EMPTY (1 << 16)
#define FLASH_ACR_ICEN (1 << 9) /** FLASH_ACR_ICRST Instruction cache reset **/
#define FLASH_ACR_ICRST (1 << 11)
/** FLASH_ACR_ICEN Instruction cache enable **/
#define FLASH_ACR_ICEN (1 << 9)
/** FLASH_ACR_PRFTEN Prefetch enable **/
#define FLASH_ACR_PRFTEN (1 << 8) #define FLASH_ACR_PRFTEN (1 << 8)
#define FLASH_ACR_LATENCY_SHIFT 0 #define FLASH_ACR_LATENCY_SHIFT 0
@ -67,59 +74,116 @@
#define FLASH_ACR_LATENCY_2WS 0x02 #define FLASH_ACR_LATENCY_2WS 0x02
/**@}*/ /**@}*/
/* --- FLASH_KEYR values ---------------------------------------------------- */ /**@}*/
/** @defgroup flash_keyr KEYR Flash key register
@{*/
/** FLASH_KEYR_KEY1 Flash key 1 **/
#define FLASH_KEYR_KEY1 ((uint32_t)0x08192a3b) #define FLASH_KEYR_KEY1 ((uint32_t)0x08192a3b)
/** FLASH_KEYR_KEY2 Flash key 2 **/
#define FLASH_KEYR_KEY2 ((uint32_t)0x4c5d6e7f) #define FLASH_KEYR_KEY2 ((uint32_t)0x4c5d6e7f)
/**@}*/
/** @defgroup flash_optkeyr OPTKEYR Option byte key register
@{*/
/** FLASH_OPTKEYR_KEY1 Option key 1 **/
#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 #define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1
/** FLASH_OPTKEYR_KEY2 Option key 2 **/
#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 #define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2
/* --- FLASH_SR values ------------------------------------------------------ */ /**@}*/
/** @defgroup flash_sr SR Status register
@{*/
/** FLASH_SR_CFGBSY Programming or erase configuration busy. **/
#define FLASH_SR_CFGBSY (1 << 18) #define FLASH_SR_CFGBSY (1 << 18)
/** FLASH_SR_BSY Busy **/
#define FLASH_SR_BSY (1 << 16) #define FLASH_SR_BSY (1 << 16)
/** FLASH_SR_OPTVERR Option and Engineering bits loading validity error **/
#define FLASH_SR_OPTVERR (1 << 15) #define FLASH_SR_OPTVERR (1 << 15)
/** FLASH_SR_RDERR PCROP read error **/
#define FLASH_SR_RDERR (1 << 14) #define FLASH_SR_RDERR (1 << 14)
/** FLASH_SR_FASTERR Fast programming error **/
#define FLASH_SR_FASTERR (1 << 9) #define FLASH_SR_FASTERR (1 << 9)
/** FLASH_SR_MISERR Fast programming data miss error **/
#define FLASH_SR_MISERR (1 << 8) #define FLASH_SR_MISERR (1 << 8)
/** FLASH_SR_PGSERR Programming sequence error **/
#define FLASH_SR_PGSERR (1 << 7) #define FLASH_SR_PGSERR (1 << 7)
/** FLASH_SR_SIZERR Size error **/
#define FLASH_SR_SIZERR (1 << 6) #define FLASH_SR_SIZERR (1 << 6)
/** FLASH_SR_PGAERR Programming alignment error **/
#define FLASH_SR_PGAERR (1 << 5) #define FLASH_SR_PGAERR (1 << 5)
/** FLASH_SR_WRPERR Write protected error **/
#define FLASH_SR_WRPERR (1 << 4) #define FLASH_SR_WRPERR (1 << 4)
/** FLASH_SR_PROGERR Programming error **/
#define FLASH_SR_PROGERR (1 << 3) #define FLASH_SR_PROGERR (1 << 3)
/** FLASH_SR_OPERR Operation error **/
#define FLASH_SR_OPERR (1 << 1) #define FLASH_SR_OPERR (1 << 1)
/** FLASH_SR_EOP End of operation **/
#define FLASH_SR_EOP (1 << 0) #define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ------------------------------------------------------ */ /**@}*/
/** @defgroup flash_cr CR Flash control register
@{*/
/** FLASH_CR_LOCK FLASH_CR Lock **/
#define FLASH_CR_LOCK (1 << 31) #define FLASH_CR_LOCK (1 << 31)
/** FLASH_CR_OPTLOCK Options Lock **/
#define FLASH_CR_OPTLOCK (1 << 30) #define FLASH_CR_OPTLOCK (1 << 30)
/** FLASH_CR_SEC_PROT Securable memory area protection enable **/
#define FLASH_CR_SEC_PROT (1 << 28) #define FLASH_CR_SEC_PROT (1 << 28)
/** FLASH_CR_OBL_LAUNCH Force the option byte loading **/
#define FLASH_CR_OBL_LAUNCH (1 << 27) #define FLASH_CR_OBL_LAUNCH (1 << 27)
/** FLASH_CR_RDERRIE PCROP read error interrupt enable **/
#define FLASH_CR_RDERRIE (1 << 26) #define FLASH_CR_RDERRIE (1 << 26)
/** FLASH_CR_ERRIE Error interrupt enable **/
#define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_ERRIE (1 << 25)
/** FLASH_CR_EOPIE End of operation interrupt enable **/
#define FLASH_CR_EOPIE (1 << 24) #define FLASH_CR_EOPIE (1 << 24)
/** FLASH_CR_FSTPG Fast programming **/
#define FLASH_CR_FSTPG (1 << 18) #define FLASH_CR_FSTPG (1 << 18)
/** FLASH_CR_OPTSTRT Options modification start **/
#define FLASH_CR_OPTSTRT (1 << 17) #define FLASH_CR_OPTSTRT (1 << 17)
#define FLASH_CR_STRT (1 << 16) /** FLASH_CR_STRT Start **/
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_PNB_SHIFT 3 #define FLASH_CR_PNB_SHIFT 3
#define FLASH_CR_PNB_MASK 0x3f #define FLASH_CR_PNB_MASK 0x3f
/** FLASH_CR_MER Mass erase **/
#define FLASH_CR_MER (1 << 2) #define FLASH_CR_MER (1 << 2)
/** FLASH_CR_PER Page erase **/
#define FLASH_CR_PER (1 << 1) #define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0) /** FLASH_CR_PG Programming **/
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_ECCR values ---------------------------------------------------- */ /**@}*/
/** @defgroup flash_eccr ECCR Flash ECC register
@{*/
/** FLASH_ECCR_ECCD ECC detection **/
#define FLASH_ECCR_ECCD (1 << 31) #define FLASH_ECCR_ECCD (1 << 31)
/** FLASH_ECCR_ECCC ECC correction **/
#define FLASH_ECCR_ECCC (1 << 30) #define FLASH_ECCR_ECCC (1 << 30)
/** FLASH_ECCR_ECCIE ECC correction interrupt enable **/
#define FLASH_ECCR_ECCIE (1 << 24) #define FLASH_ECCR_ECCIE (1 << 24)
/** FLASH_ECCR_SYSF_ECC ECC fail for Corrected ECC Error or Double ECC Error in info block **/
#define FLASH_ECCR_SYSF_ECC (1 << 20) #define FLASH_ECCR_SYSF_ECC (1 << 20)
#define FLASH_ECCR_ADDR_ECC_SHIFT 0 #define FLASH_ECCR_ADDR_ECC_SHIFT 0
#define FLASH_ECCR_ADDR_ECC_MASK 0x3fff #define FLASH_ECCR_ADDR_ECC_MASK 0x3fff
/* --- FLASH_OPTR values ---------------------------------------------------- */
/**@}*/
/** @defgroup flash_optr OPTR Flash option register
@{*/
/** FLASH_OPTR_IRHEN Internal reset holder enable bit **/
#define FLASH_OPTR_IRHEN (1 << 29) #define FLASH_OPTR_IRHEN (1 << 29)
#define FLASH_OPTR_NRST_MODE_SHIFT 27 #define FLASH_OPTR_NRST_MODE_SHIFT 27
@ -132,17 +196,28 @@
#define FLASH_OPTR_NRST_MODE_BIDIR 3 #define FLASH_OPTR_NRST_MODE_BIDIR 3
/**@}*/ /**@}*/
/** FLASH_OPTR_nBOOT0 nBOOT0 option bit **/
#define FLASH_OPTR_nBOOT0 (1 << 26) #define FLASH_OPTR_nBOOT0 (1 << 26)
/** FLASH_OPTR_nBOOT1 Boot configuration **/
#define FLASH_OPTR_nBOOT1 (1 << 25) #define FLASH_OPTR_nBOOT1 (1 << 25)
#define FLASH_OPTR_nBOOT_SEL (1 << 24) /** FLASH_OPTR_nBOOT_SEL nBOOT_SEL **/
#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22) #define FLASH_OPTR_nBOOT_SEL (1 << 24)
/** FLASH_OPTR_RAM_PARITY_CHECK SRAM parity check control **/
#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22)
/** FLASH_OPTR_WWDG_SW Window watchdog selection **/
#define FLASH_OPTR_WWDG_SW (1 << 19) #define FLASH_OPTR_WWDG_SW (1 << 19)
#define FLASH_OPTR_IWDG_STDBY (1 << 18) /** FLASH_OPTR_IWDG_STDBY Independent watchdog counter freeze in Standby mode **/
#define FLASH_OPTR_IWDG_STOP (1 << 17) #define FLASH_OPTR_IWDG_STDBY (1 << 18)
/** FLASH_OPTR_IWDG_STOP Independent watchdog counter freeze in Stop mode **/
#define FLASH_OPTR_IWDG_STOP (1 << 17)
/** FLASH_OPTR_IDWG_SW Independent watchdog selection **/
#define FLASH_OPTR_IDWG_SW (1 << 16) #define FLASH_OPTR_IDWG_SW (1 << 16)
#define FLASH_OPTR_nRSTS_HDW (1 << 15) /** FLASH_OPTR_nRSTS_HDW nRSTS_HDW **/
#define FLASH_OPTR_nRST_STDBY (1 << 14) #define FLASH_OPTR_nRSTS_HDW (1 << 15)
#define FLASH_OPTR_nRST_STOP (1 << 13) /** FLASH_OPTR_nRST_STDBY nRST_STDBY **/
#define FLASH_OPTR_nRST_STDBY (1 << 14)
/** FLASH_OPTR_nRST_STOP nRST_STOP **/
#define FLASH_OPTR_nRST_STOP (1 << 13)
#define FLASH_OPTR_BORR_LEV_SHIFT 11 #define FLASH_OPTR_BORR_LEV_SHIFT 11
#define FLASH_OPTR_BORR_LEV_MASK 0x03 #define FLASH_OPTR_BORR_LEV_MASK 0x03
@ -166,6 +241,7 @@
#define FLASH_OPTR_BORF_LEV_2V8 3 #define FLASH_OPTR_BORF_LEV_2V8 3
/**@}*/ /**@}*/
/** FLASH_OPTR_BOREN BOR reset Level **/
#define FLASH_OPTR_BOREN (1 << 8) #define FLASH_OPTR_BOREN (1 << 8)
#define FLASH_OPTR_RDP_SHIFT 0 #define FLASH_OPTR_RDP_SHIFT 0
@ -178,6 +254,8 @@
#define FLASH_OPTR_RDP_LEVEL_2 0xCC #define FLASH_OPTR_RDP_LEVEL_2 0xCC
/**@}*/ /**@}*/
/**@}*/
BEGIN_DECLS BEGIN_DECLS
/** Enable instruction cache */ /** Enable instruction cache */