More progress towards L1 support.
Believe gpio is complete, but untested without finishing at least the RCC defines. RCC defines are a work in progress
This commit is contained in:
Karl Palsson
parent
2011941b55
commit
8318384cf1
2
Makefile
2
Makefile
@ -32,7 +32,7 @@ SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts
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INSTALL = install
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SRCLIBDIR = $(shell pwd)/lib
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TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg
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TARGETS = stm32/f1 stm32/f2 stm32/f4 stm32/l1 lpc13xx lpc17xx lpc43xx lm3s efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg
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# Be silent per default, but 'make V=1' will show all compiler calls.
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ifneq ($(V),1)
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165
examples/stm32/l1/Makefile.include
Normal file
165
examples/stm32/l1/Makefile.include
Normal file
@ -0,0 +1,165 @@
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##
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## This file is part of the libopencm3 project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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## Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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##
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## This library is free software: you can redistribute it and/or modify
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## it under the terms of the GNU Lesser General Public License as published by
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## the Free Software Foundation, either version 3 of the License, or
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## (at your option) any later version.
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##
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## This library is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU Lesser General Public License for more details.
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##
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## You should have received a copy of the GNU Lesser General Public License
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## along with this library. If not, see <http://www.gnu.org/licenses/>.
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##
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PREFIX ?= arm-none-eabi
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#PREFIX ?= arm-elf
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CC = $(PREFIX)-gcc
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LD = $(PREFIX)-gcc
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OBJCOPY = $(PREFIX)-objcopy
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OBJDUMP = $(PREFIX)-objdump
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GDB = $(PREFIX)-gdb
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# If you are copying this file to use in your own project,
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# You will need to change this... (Leave unset to assume installed
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# in the toolchain itself)
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#OPENCM3_DIR ?= /opt/libopencm3/$(PREFIX)
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OPENCM3_DIR ?= ../../../../..
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ARCH_FLAGS = -mcpu=cortex-m3 -mthumb -msoft-float
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CFLAGS += -g -Os -Wall -Wextra \
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-fno-common $(ARCH_FLAGS) -MD -DSTM32L1
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LDSCRIPT ?= $(BINARY).ld
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LDFLAGS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
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$(ARCH_FLAGS) -mfix-cortex-m3-ldrd
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ifneq ($(OPENCM3_DIR),)
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CFLAGS += -I$(OPENCM3_DIR)/include
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LDFLAGS += -L$(OPENCM3_DIR)/lib -L$(OPENCM3_DIR)/lib/stm32/l1
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SCRIPT_DIR = $(OPENCM3_DIR)/share
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else
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SCRIPT_DIR = $(shell dirname $(shell readlink -f $(shell which $(PREFIX)-gcc)))/../$(PREFIX)/share
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endif
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OBJS += $(BINARY).o
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OOCD ?= openocd
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OOCD_INTERFACE ?= flossjtag
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OOCD_BOARD ?= olimex_stm32_h103
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# Black magic probe specific variables
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# Set the BMP_PORT to a serial port and then BMP is used for flashing
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BMP_PORT ?=
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# texane/stlink can be used by uncommenting this...
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# or defining it in your own makefiles
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#STLINK_PORT ?= :4242
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# Be silent per default, but 'make V=1' will show all compiler calls.
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ifneq ($(V),1)
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Q := @
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NULL := 2>/dev/null
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else
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LDFLAGS += -Wl,--print-gc-sections
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endif
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.SUFFIXES: .elf .bin .hex .srec .list .images
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.SECONDEXPANSION:
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.SECONDARY:
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all: images
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images: $(BINARY).images
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flash: $(BINARY).flash
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%.images: %.bin %.hex %.srec %.list
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@#echo "*** $* images generated ***"
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%.bin: %.elf
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@#printf " OBJCOPY $(*).bin\n"
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$(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin
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%.hex: %.elf
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@#printf " OBJCOPY $(*).hex\n"
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$(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex
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%.srec: %.elf
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@#printf " OBJCOPY $(*).srec\n"
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$(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec
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%.list: %.elf
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@#printf " OBJDUMP $(*).list\n"
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$(Q)$(OBJDUMP) -S $(*).elf > $(*).list
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ifeq ($(OPENCM3_DIR),)
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%.elf: $(OBJS) $(LDSCRIPT)
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else
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%.elf: $(OBJS) $(LDSCRIPT) $(OPENCM3_DIR)/lib/stm32/l1/libopencm3_stm32l1.a
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endif
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@#printf " LD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32l1 $(LDFLAGS)
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%.o: %.c Makefile
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@#printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) $(CFLAGS) -o $@ -c $<
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clean:
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$(Q)rm -f *.o
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$(Q)rm -f *.d
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$(Q)rm -f *.elf
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$(Q)rm -f *.bin
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$(Q)rm -f *.hex
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$(Q)rm -f *.srec
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$(Q)rm -f *.list
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ifeq ($(STLINK_PORT),)
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ifeq ($(BMP_PORT),)
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ifeq ($(OOCD_SERIAL),)
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%.flash: %.hex
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@printf " FLASH $<\n"
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@# IMPORTANT: Don't use "resume", only "reset" will work correctly!
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$(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \
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-f board/$(OOCD_BOARD).cfg \
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-c "init" -c "reset init" \
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-c "stm32l1x mass_erase 0" \
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-c "flash write_image $(*).hex" \
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-c "reset" \
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-c "shutdown" $(NULL)
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else
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%.flash: %.hex
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@printf " FLASH $<\n"
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@# IMPORTANT: Don't use "resume", only "reset" will work correctly!
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$(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \
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-f board/$(OOCD_BOARD).cfg \
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-c "ft2232_serial $(OOCD_SERIAL)" \
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-c "init" -c "reset init" \
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-c "stm32l1x mass_erase 0" \
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-c "flash write_image $(*).hex" \
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-c "reset" \
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-c "shutdown" $(NULL)
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endif
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else
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%.flash: %.elf
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@echo " GDB $(*).elf (flash)"
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$(Q)$(GDB) --batch \
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-ex 'target extended-remote $(BMP_PORT)' \
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-x $(TOOLCHAIN_DIR)/scripts/black_magic_probe_flash.scr \
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$(*).elf
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endif
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else
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%.flash: %.elf
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@echo " GDB $(*).elf (flash)"
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$(Q)$(GDB) --batch \
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-ex 'target extended-remote $(STLINK_PORT)' \
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-x $(SCRIPT_DIR)/libopencm3/scripts/stlink_flash.scr \
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$(*).elf
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endif
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.PHONY: images clean
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-include $(OBJS:.o=.d)
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25
examples/stm32/l1/stm32l-discovery/miniblink/Makefile
Normal file
25
examples/stm32/l1/stm32l-discovery/miniblink/Makefile
Normal file
@ -0,0 +1,25 @@
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##
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## This file is part of the libopencm3 project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This library is free software: you can redistribute it and/or modify
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## it under the terms of the GNU Lesser General Public License as published by
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## the Free Software Foundation, either version 3 of the License, or
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## (at your option) any later version.
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##
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## This library is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU Lesser General Public License for more details.
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##
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## You should have received a copy of the GNU Lesser General Public License
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## along with this library. If not, see <http://www.gnu.org/licenses/>.
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##
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BINARY = miniblink
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LDSCRIPT = ../stm32l15xxB.ld
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include ../../Makefile.include
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9
examples/stm32/l1/stm32l-discovery/miniblink/README
Normal file
9
examples/stm32/l1/stm32l-discovery/miniblink/README
Normal file
@ -0,0 +1,9 @@
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------------------------------------------------------------------------------
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README
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------------------------------------------------------------------------------
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This is the smallest-possible example program using libopencm3.
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It's intended for the ST STM32L-DISCOVERY eval board. It should blink
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the blue LED on the board.
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72
examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c
Normal file
72
examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c
Normal file
@ -0,0 +1,72 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/l1/rcc.h>
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#include <libopencm3/stm32/l1/gpio.h>
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#define PORT_LED GPIOB
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#define PIN_LED GPIO6
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void gpio_setup(void)
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{
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/* Enable GPIOB clock. */
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/* Manually: */
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RCC_AHBENR |= RCC_AHBENR_IOPBEN;
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/* Using API functions: */
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//rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN);
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/* Set GPIO6 (in GPIO port B) to 'output push-pull'. */
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/* Using API functions: */
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gpio_mode_setup(PORT_LED, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, PIN_LED);
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}
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int main(void)
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{
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int i;
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gpio_setup();
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/* Blink the LED (PC8) on the board. */
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while (1) {
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/* Manually: */
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// GPIOD_BSRR = GPIO12; /* LED off */
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// for (i = 0; i < 1000000; i++) /* Wait a bit. */
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// __asm__("nop");
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// GPIOD_BRR = GPIO12; /* LED on */
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// for (i = 0; i < 1000000; i++) /* Wait a bit. */
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// __asm__("nop");
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/* Using API functions gpio_set()/gpio_clear(): */
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// gpio_set(GPIOD, GPIO12); /* LED off */
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// for (i = 0; i < 1000000; i++) /* Wait a bit. */
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// __asm__("nop");
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// gpio_clear(GPIOD, GPIO12); /* LED on */
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// for (i = 0; i < 1000000; i++) /* Wait a bit. */
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// __asm__("nop");
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/* Using API function gpio_toggle(): */
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gpio_toggle(PORT_LED, PORT_LED); /* LED on/off */
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for (i = 0; i < 1000000; i++) /* Wait a bit. */
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__asm__("nop");
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}
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return 0;
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}
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241
include/libopencm3/stm32/l1/gpio.h
Normal file
241
include/libopencm3/stm32/l1/gpio.h
Normal file
@ -0,0 +1,241 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
|
||||
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_GPIO_H
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#define LIBOPENCM3_GPIO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPIO port base addresses (for convenience) */
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#define GPIOA GPIO_PORT_A_BASE
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#define GPIOB GPIO_PORT_B_BASE
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#define GPIOC GPIO_PORT_C_BASE
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#define GPIOD GPIO_PORT_D_BASE
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#define GPIOE GPIO_PORT_E_BASE
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#define GPIOH GPIO_PORT_H_BASE
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/* GPIO number definitions (for convenience) */
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/* --- GPIO registers ------------------------------------------------------ */
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/* Port mode register (GPIOx_MODER) */
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#define GPIO_MODER(port) MMIO32(port + 0x00)
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#define GPIOA_MODER GPIO_MODER(GPIOA)
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#define GPIOB_MODER GPIO_MODER(GPIOB)
|
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#define GPIOC_MODER GPIO_MODER(GPIOC)
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#define GPIOD_MODER GPIO_MODER(GPIOD)
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#define GPIOE_MODER GPIO_MODER(GPIOE)
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#define GPIOH_MODER GPIO_MODER(GPIOH)
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|
||||
/* Port output type register (GPIOx_OTYPER) */
|
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#define GPIO_OTYPER(port) MMIO32(port + 0x04)
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#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
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#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
|
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#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
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#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
|
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#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
|
||||
#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
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||||
|
||||
/* Port output speed register (GPIOx_OSPEEDR) */
|
||||
#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
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#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
|
||||
#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
|
||||
#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
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||||
#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
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||||
#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
|
||||
#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
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||||
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||||
/* Port pull-up/pull-down register (GPIOx_PUPDR) */
|
||||
#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
|
||||
#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
|
||||
#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
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||||
#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
|
||||
#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
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||||
#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
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||||
#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
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||||
|
||||
/* Port input data register (GPIOx_IDR) */
|
||||
#define GPIO_IDR(port) MMIO32(port + 0x10)
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||||
#define GPIOA_IDR GPIO_IDR(GPIOA)
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||||
#define GPIOB_IDR GPIO_IDR(GPIOB)
|
||||
#define GPIOC_IDR GPIO_IDR(GPIOC)
|
||||
#define GPIOD_IDR GPIO_IDR(GPIOD)
|
||||
#define GPIOE_IDR GPIO_IDR(GPIOE)
|
||||
#define GPIOH_IDR GPIO_IDR(GPIOH)
|
||||
|
||||
/* Port output data register (GPIOx_ODR) */
|
||||
#define GPIO_ODR(port) MMIO32(port + 0x14)
|
||||
#define GPIOA_ODR GPIO_ODR(GPIOA)
|
||||
#define GPIOB_ODR GPIO_ODR(GPIOB)
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||||
#define GPIOC_ODR GPIO_ODR(GPIOC)
|
||||
#define GPIOD_ODR GPIO_ODR(GPIOD)
|
||||
#define GPIOE_ODR GPIO_ODR(GPIOE)
|
||||
#define GPIOH_ODR GPIO_ODR(GPIOH)
|
||||
|
||||
/* Port bit set/reset register (GPIOx_BSRR) */
|
||||
#define GPIO_BSRR(port) MMIO32(port + 0x18)
|
||||
#define GPIOA_BSRR GPIO_BSRR(GPIOA)
|
||||
#define GPIOB_BSRR GPIO_BSRR(GPIOB)
|
||||
#define GPIOC_BSRR GPIO_BSRR(GPIOC)
|
||||
#define GPIOD_BSRR GPIO_BSRR(GPIOD)
|
||||
#define GPIOE_BSRR GPIO_BSRR(GPIOE)
|
||||
#define GPIOH_BSRR GPIO_BSRR(GPIOH)
|
||||
|
||||
/* Port configuration lock register (GPIOx_LCKR) */
|
||||
#define GPIO_LCKR(port) MMIO32(port + 0x1C)
|
||||
#define GPIOA_LCKR GPIO_LCKR(GPIOA)
|
||||
#define GPIOB_LCKR GPIO_LCKR(GPIOB)
|
||||
#define GPIOC_LCKR GPIO_LCKR(GPIOC)
|
||||
#define GPIOD_LCKR GPIO_LCKR(GPIOD)
|
||||
#define GPIOE_LCKR GPIO_LCKR(GPIOE)
|
||||
#define GPIOH_LCKR GPIO_LCKR(GPIOH)
|
||||
|
||||
/* Alternate function low register (GPIOx_AFRL) */
|
||||
#define GPIO_AFRL(port) MMIO32(port + 0x20)
|
||||
#define GPIOA_AFRL GPIO_AFRL(GPIOA)
|
||||
#define GPIOB_AFRL GPIO_AFRL(GPIOB)
|
||||
#define GPIOC_AFRL GPIO_AFRL(GPIOC)
|
||||
#define GPIOD_AFRL GPIO_AFRL(GPIOD)
|
||||
#define GPIOE_AFRL GPIO_AFRL(GPIOE)
|
||||
#define GPIOH_AFRL GPIO_AFRL(GPIOH)
|
||||
|
||||
/* Alternate function high register (GPIOx_AFRH) */
|
||||
#define GPIO_AFRH(port) MMIO32(port + 0x24)
|
||||
#define GPIOA_AFRH GPIO_AFRH(GPIOA)
|
||||
#define GPIOB_AFRH GPIO_AFRH(GPIOB)
|
||||
#define GPIOC_AFRH GPIO_AFRH(GPIOC)
|
||||
#define GPIOD_AFRH GPIO_AFRH(GPIOD)
|
||||
#define GPIOE_AFRH GPIO_AFRH(GPIOE)
|
||||
#define GPIOH_AFRH GPIO_AFRH(GPIOH)
|
||||
|
||||
/* --- GPIOx_MODER values-------------------------------------------- */
|
||||
|
||||
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
|
||||
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_MODE_INPUT 0x00 /* Default */
|
||||
#define GPIO_MODE_OUTPUT 0x01
|
||||
#define GPIO_MODE_ALTFN 0x02
|
||||
#define GPIO_MODE_ANALOG 0x03
|
||||
|
||||
/* --- GPIOx_OTYPER values -------------------------------------------- */
|
||||
/* Output type (OTx values) */
|
||||
#define GPIO_OTYPE_PP 0x0
|
||||
#define GPIO_OTYPE_OD 0x1
|
||||
|
||||
/* Output speed values */
|
||||
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_OSPEED_400KHZ 0x0
|
||||
#define GPIO_OSPEED_2MHZ 0x1
|
||||
#define GPIO_OSPEED_10MHZ 0x2
|
||||
#define GPIO_OSPEED_40MHZ 0x3
|
||||
|
||||
/* --- GPIOx_PUPDR values ------------------------------------------- */
|
||||
|
||||
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
|
||||
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
|
||||
#define GPIO_PUPD_NONE 0x0
|
||||
#define GPIO_PUPD_PULLUP 0x1
|
||||
#define GPIO_PUPD_PULLDOWN 0x2
|
||||
|
||||
/* --- GPIO_IDR values ----------------------------------------------------- */
|
||||
|
||||
/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
|
||||
|
||||
/* --- GPIO_ODR values ----------------------------------------------------- */
|
||||
|
||||
/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
|
||||
|
||||
/* --- GPIO_BSRR values ---------------------------------------------------- */
|
||||
|
||||
/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
|
||||
/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
|
||||
|
||||
/* --- GPIO_LCKR values ---------------------------------------------------- */
|
||||
|
||||
#define GPIO_LCKK (1 << 16)
|
||||
/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
|
||||
|
||||
/* --- GPIOx_AFRL/H values ------------------------------------------------- */
|
||||
|
||||
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
|
||||
/* See datasheet table 5, page 35 for the definitions */
|
||||
|
||||
#define GPIO_AFR(n, af) (af << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
|
||||
#define GPIO_AF0 0x0
|
||||
#define GPIO_AF1 0x1
|
||||
#define GPIO_AF2 0x2
|
||||
#define GPIO_AF3 0x3
|
||||
#define GPIO_AF4 0x4
|
||||
#define GPIO_AF5 0x5
|
||||
#define GPIO_AF6 0x6
|
||||
#define GPIO_AF7 0x7
|
||||
#define GPIO_AF8 0x8
|
||||
#define GPIO_AF9 0x9
|
||||
#define GPIO_AF10 0xa
|
||||
#define GPIO_AF11 0xb
|
||||
#define GPIO_AF12 0xc
|
||||
#define GPIO_AF13 0xd
|
||||
#define GPIO_AF14 0xe
|
||||
#define GPIO_AF15 0xf
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* L1, like F2 and F4, has the "new" GPIO peripheral, so use that style
|
||||
* TODO: this should all really be moved to a "common" gpio header
|
||||
*/
|
||||
|
||||
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
|
||||
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
|
||||
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
|
||||
|
||||
/* F1 compatible api */
|
||||
void gpio_set(u32 gpioport, u16 gpios);
|
||||
void gpio_clear(u32 gpioport, u16 gpios);
|
||||
u16 gpio_get(u32 gpioport, u16 gpios);
|
||||
void gpio_toggle(u32 gpioport, u16 gpios);
|
||||
u16 gpio_port_read(u32 gpioport);
|
||||
void gpio_port_write(u32 gpioport, u16 data);
|
||||
void gpio_port_config_lock(u32 gpioport, u16 gpios);
|
||||
|
||||
#endif
|
||||
453
include/libopencm3/stm32/l1/rcc.h
Normal file
453
include/libopencm3/stm32/l1/rcc.h
Normal file
@ -0,0 +1,453 @@
|
||||
/** @file
|
||||
|
||||
@ingroup STM32L1xx
|
||||
|
||||
@brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
|
||||
@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
|
||||
|
||||
@date 18 May 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/** @defgroup STM32L1xx_rcc_defines
|
||||
|
||||
@brief Defined Constants and Types for the STM32L1xx Reset and Clock Control
|
||||
|
||||
@ingroup STM32L1xx_defines
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
|
||||
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Originally based on the F1 code, as it seemed most similar to the L1
|
||||
* TODO: very incomplete still!
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_RCC_H
|
||||
#define LIBOPENCM3_RCC_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- RCC registers ------------------------------------------------------- */
|
||||
|
||||
#define RCC_CR MMIO32(RCC_BASE + 0x00)
|
||||
#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
|
||||
#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
|
||||
#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
|
||||
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)
|
||||
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)
|
||||
#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)
|
||||
#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)
|
||||
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)
|
||||
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)
|
||||
#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)
|
||||
#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)
|
||||
#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)
|
||||
#define RCC_CSR MMIO32(RCC_BASE + 0x34)
|
||||
|
||||
/* --- RCC_CR values ------------------------------------------------------- */
|
||||
|
||||
/* RTCPRE[1:0] at 30:29 */
|
||||
#define RCC_CR_CSSON (1 << 28)
|
||||
#define RCC_CR_PLLRDY (1 << 25)
|
||||
#define RCC_CR_PLLON (1 << 24)
|
||||
#define RCC_CR_HSEBYP (1 << 18)
|
||||
#define RCC_CR_HSERDY (1 << 17)
|
||||
#define RCC_CR_HSEON (1 << 16)
|
||||
#define RCC_CR_MSIRDY (1 << 9)
|
||||
#define RCC_CR_MSION (1 << 8)
|
||||
#define RCC_CR_HSIRDY (1 << 1)
|
||||
#define RCC_CR_HSION (1 << 0)
|
||||
|
||||
/* --- RCC_ICSCR values ---------------------------------------------------- */
|
||||
|
||||
// TODO
|
||||
|
||||
/* --- RCC_CFGR values ----------------------------------------------------- */
|
||||
|
||||
/* MCOPRE */
|
||||
#define RCC_CFGR_MCOPRE_DIV1 0
|
||||
#define RCC_CFGR_MCOPRE_DIV2 1
|
||||
#define RCC_CFGR_MCOPRE_DIV4 2
|
||||
#define RCC_CFGR_MCOPRE_DIV8 3
|
||||
#define RCC_CFGR_MCOPRE_DIV16 4
|
||||
|
||||
/* MCO: Microcontroller clock output */
|
||||
#define RCC_CFGR_MCO_NOCLK 0x0
|
||||
#define RCC_CFGR_MCO_SYSCLK 0x1
|
||||
#define RCC_CFGR_MCO_HSICLK 0x2
|
||||
#define RCC_CFGR_MCO_MSICLK 0x3
|
||||
#define RCC_CFGR_MCO_HSECLK 0x4
|
||||
#define RCC_CFGR_MCO_PLLCLK 0x5
|
||||
#define RCC_CFGR_MCO_LSICLK 0x6
|
||||
#define RCC_CFGR_MCO_LSECLK 0x7
|
||||
|
||||
/* PLL Output division selection */
|
||||
#define RCC_CFGR_PLLDIV_DIV2 0x1
|
||||
#define RCC_CFGR_PLLDIV_DIV3 0x2
|
||||
#define RCC_CFGR_PLLDIV_DIV4 0x3
|
||||
|
||||
/* PLLMUL: PLL multiplication factor */
|
||||
#define RCC_CFGR_PLLMUL_MUL3 0x0
|
||||
#define RCC_CFGR_PLLMUL_MUL4 0x1
|
||||
#define RCC_CFGR_PLLMUL_MUL6 0x2
|
||||
#define RCC_CFGR_PLLMUL_MUL8 0x3
|
||||
#define RCC_CFGR_PLLMUL_MUL12 0x4
|
||||
#define RCC_CFGR_PLLMUL_MUL16 0x5
|
||||
#define RCC_CFGR_PLLMUL_MUL24 0x6
|
||||
#define RCC_CFGR_PLLMUL_MUL32 0x7
|
||||
#define RCC_CFGR_PLLMUL_MUL48 0x8
|
||||
|
||||
/* PLLSRC: PLL entry clock source */
|
||||
#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
|
||||
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
|
||||
|
||||
/* PPRE2: APB high-speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
|
||||
|
||||
/* PPRE1: APB low-speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
|
||||
|
||||
/* HPRE: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
|
||||
|
||||
/* SWS: System clock switch status */
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
|
||||
|
||||
/* SW: System clock switch */
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
|
||||
|
||||
/* --- RCC_CIR values ------------------------------------------------------ */
|
||||
|
||||
/* Clock security system interrupt clear bit */
|
||||
#define RCC_CIR_CSSC (1 << 23)
|
||||
|
||||
/* OSC ready interrupt clear bits */
|
||||
#define RCC_CIR_MSIRDYC (1 << 21)
|
||||
#define RCC_CIR_PLLRDYC (1 << 20)
|
||||
#define RCC_CIR_HSERDYC (1 << 19)
|
||||
#define RCC_CIR_HSIRDYC (1 << 18)
|
||||
#define RCC_CIR_LSERDYC (1 << 17)
|
||||
#define RCC_CIR_LSIRDYC (1 << 16)
|
||||
|
||||
/* OSC ready interrupt enable bits */
|
||||
#define RCC_CIR_MSIRDYIE (1 << 13)
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12)
|
||||
#define RCC_CIR_HSERDYIE (1 << 11)
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10)
|
||||
#define RCC_CIR_LSERDYIE (1 << 9)
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8)
|
||||
|
||||
/* Clock security system interrupt flag bit */
|
||||
#define RCC_CIR_CSSF (1 << 7)
|
||||
|
||||
/* OSC ready interrupt flag bits */
|
||||
#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */
|
||||
#define RCC_CIR_PLLRDYF (1 << 4)
|
||||
#define RCC_CIR_HSERDYF (1 << 3)
|
||||
#define RCC_CIR_HSIRDYF (1 << 2)
|
||||
#define RCC_CIR_LSERDYF (1 << 1)
|
||||
#define RCC_CIR_LSIRDYF (1 << 0)
|
||||
|
||||
/* --- RCC_AHBRSTR values ------------------------------------------------- */
|
||||
#define RCC_AHBRSTR_DMA1RST (1 << 24)
|
||||
#define RCC_AHBRSTR_FLITFRST (1 << 15)
|
||||
#define RCC_AHBRSTR_CRCRST (1 << 12)
|
||||
#define RCC_AHBRSTR_GPIOHRST (1 << 5)
|
||||
#define RCC_AHBRSTR_GPIOERST (1 << 4)
|
||||
#define RCC_AHBRSTR_GPIODRST (1 << 3)
|
||||
#define RCC_AHBRSTR_GPIOCRST (1 << 2)
|
||||
#define RCC_AHBRSTR_GPIOBRST (1 << 1)
|
||||
#define RCC_AHBRSTR_GPIOARST (1 << 0)
|
||||
|
||||
/* --- RCC_APB2RSTR values ------------------------------------------------- */
|
||||
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14)
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12)
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9)
|
||||
#define RCC_APB2RSTR_TIM11RST (1 << 4)
|
||||
#define RCC_APB2RSTR_TIM10RST (1 << 3)
|
||||
#define RCC_APB2RSTR_TIM9RST (1 << 2)
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
|
||||
|
||||
/* --- RCC_APB1RSTR values ------------------------------------------------- */
|
||||
|
||||
TODO : up to here
|
||||
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29)
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28)
|
||||
#define RCC_APB1RSTR_BKPRST (1 << 27)
|
||||
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
|
||||
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
|
||||
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
|
||||
#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22)
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21)
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20)
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19)
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18)
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17)
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15)
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14)
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11)
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5)
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4)
|
||||
#define RCC_APB1RSTR_TIM5RST (1 << 3)
|
||||
#define RCC_APB1RSTR_TIM4RST (1 << 2)
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1)
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0)
|
||||
|
||||
/* --- RCC_AHBENR values --------------------------------------------------- */
|
||||
|
||||
/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
|
||||
@ingroup STM32L1xx_rcc_defines
|
||||
|
||||
@{*/
|
||||
#define RCC_AHBENR_ETHMACENRX (1 << 16)
|
||||
#define RCC_AHBENR_ETHMACENTX (1 << 15)
|
||||
#define RCC_AHBENR_ETHMACEN (1 << 14)
|
||||
#define RCC_AHBENR_OTGFSEN (1 << 12)
|
||||
#define RCC_AHBENR_SDIOEN (1 << 10)
|
||||
#define RCC_AHBENR_FSMCEN (1 << 8)
|
||||
#define RCC_AHBENR_CRCEN (1 << 6)
|
||||
#define RCC_AHBENR_FLITFEN (1 << 4)
|
||||
#define RCC_AHBENR_SRAMEN (1 << 2)
|
||||
#define RCC_AHBENR_DMA2EN (1 << 1)
|
||||
#define RCC_AHBENR_DMA1EN (1 << 0)
|
||||
/*@}*/
|
||||
|
||||
/* --- RCC_APB2ENR values -------------------------------------------------- */
|
||||
|
||||
/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
|
||||
@ingroup STM32L1xx_rcc_defines
|
||||
|
||||
@{*/
|
||||
#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14)
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12)
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11)
|
||||
#define RCC_APB2ENR_ADC2EN (1 << 10)
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 9)
|
||||
#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */
|
||||
#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */
|
||||
#define RCC_APB2ENR_IOPEEN (1 << 6)
|
||||
#define RCC_APB2ENR_IOPDEN (1 << 5)
|
||||
#define RCC_APB2ENR_IOPCEN (1 << 4)
|
||||
#define RCC_APB2ENR_IOPBEN (1 << 3)
|
||||
#define RCC_APB2ENR_IOPAEN (1 << 2)
|
||||
#define RCC_APB2ENR_AFIOEN (1 << 0)
|
||||
/*@}*/
|
||||
|
||||
/* --- RCC_APB1ENR values -------------------------------------------------- */
|
||||
|
||||
/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
|
||||
@ingroup STM32L1xx_rcc_defines
|
||||
|
||||
@{*/
|
||||
#define RCC_APB1ENR_DACEN (1 << 29)
|
||||
#define RCC_APB1ENR_PWREN (1 << 28)
|
||||
#define RCC_APB1ENR_BKPEN (1 << 27)
|
||||
#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
|
||||
#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
|
||||
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
|
||||
#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22)
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21)
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20)
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19)
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18)
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17)
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15)
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14)
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11)
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5)
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4)
|
||||
#define RCC_APB1ENR_TIM5EN (1 << 3)
|
||||
#define RCC_APB1ENR_TIM4EN (1 << 2)
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1)
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0)
|
||||
/*@}*/
|
||||
|
||||
/* --- RCC_BDCR values ----------------------------------------------------- */
|
||||
|
||||
#define RCC_BDCR_BDRST (1 << 16)
|
||||
#define RCC_BDCR_RTCEN (1 << 15)
|
||||
/* RCC_BDCR[9:8]: RTCSEL */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2)
|
||||
#define RCC_BDCR_LSERDY (1 << 1)
|
||||
#define RCC_BDCR_LSEON (1 << 0)
|
||||
|
||||
/* --- RCC_CSR values ------------------------------------------------------ */
|
||||
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31)
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30)
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29)
|
||||
#define RCC_CSR_SFTRSTF (1 << 28)
|
||||
#define RCC_CSR_PORRSTF (1 << 27)
|
||||
#define RCC_CSR_PINRSTF (1 << 26)
|
||||
#define RCC_CSR_RMVF (1 << 24)
|
||||
#define RCC_CSR_LSIRDY (1 << 1)
|
||||
#define RCC_CSR_LSION (1 << 0)
|
||||
|
||||
/* --- RCC_AHBRSTR values -------------------------------------------------- */
|
||||
|
||||
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
|
||||
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
|
||||
|
||||
/* --- RCC_CFGR2 values ---------------------------------------------------- */
|
||||
|
||||
/* I2S3SRC: I2S3 clock source */
|
||||
#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0
|
||||
#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1
|
||||
|
||||
/* I2S2SRC: I2S2 clock source */
|
||||
#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0
|
||||
#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1
|
||||
|
||||
/* PREDIV1SRC: PREDIV1 entry clock source */
|
||||
#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0
|
||||
#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1
|
||||
|
||||
#define RCC_CFGR2_PLL2MUL (1 << 0)
|
||||
#define RCC_CFGR2_PREDIV2 (1 << 0)
|
||||
#define RCC_CFGR2_PREDIV1 (1 << 0)
|
||||
|
||||
/* PLL3MUL: PLL3 multiplication factor */
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf
|
||||
|
||||
/* PLL2MUL: PLL2 multiplication factor */
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
|
||||
|
||||
/* PREDIV2: PREDIV2 division factor */
|
||||
#define RCC_CFGR2_PREDIV2_NODIV 0x0
|
||||
#define RCC_CFGR2_PREDIV2_DIV2 0x1
|
||||
#define RCC_CFGR2_PREDIV2_DIV3 0x2
|
||||
#define RCC_CFGR2_PREDIV2_DIV4 0x3
|
||||
#define RCC_CFGR2_PREDIV2_DIV5 0x4
|
||||
#define RCC_CFGR2_PREDIV2_DIV6 0x5
|
||||
#define RCC_CFGR2_PREDIV2_DIV7 0x6
|
||||
#define RCC_CFGR2_PREDIV2_DIV8 0x7
|
||||
#define RCC_CFGR2_PREDIV2_DIV9 0x8
|
||||
#define RCC_CFGR2_PREDIV2_DIV10 0x9
|
||||
#define RCC_CFGR2_PREDIV2_DIV11 0xa
|
||||
#define RCC_CFGR2_PREDIV2_DIV12 0xb
|
||||
#define RCC_CFGR2_PREDIV2_DIV13 0xc
|
||||
#define RCC_CFGR2_PREDIV2_DIV14 0xd
|
||||
#define RCC_CFGR2_PREDIV2_DIV15 0xe
|
||||
#define RCC_CFGR2_PREDIV2_DIV16 0xf
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern u32 rcc_ppre1_frequency;
|
||||
extern u32 rcc_ppre2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
typedef enum {
|
||||
PLL, HSE, HSI, LSE, LSI
|
||||
} osc_t;
|
||||
|
||||
void rcc_osc_ready_int_clear(osc_t osc);
|
||||
void rcc_osc_ready_int_enable(osc_t osc);
|
||||
void rcc_osc_ready_int_disable(osc_t osc);
|
||||
int rcc_osc_ready_int_flag(osc_t osc);
|
||||
void rcc_css_int_clear(void);
|
||||
int rcc_css_int_flag(void);
|
||||
void rcc_wait_for_osc_ready(osc_t osc);
|
||||
void rcc_osc_on(osc_t osc);
|
||||
void rcc_osc_off(osc_t osc);
|
||||
void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_osc_bypass_enable(osc_t osc);
|
||||
void rcc_osc_bypass_disable(osc_t osc);
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
|
||||
void rcc_set_sysclk_source(u32 clk);
|
||||
void rcc_set_pll_multiplication_factor(u32 mul);
|
||||
void rcc_set_pll_source(u32 pllsrc);
|
||||
void rcc_set_pllxtpre(u32 pllxtpre);
|
||||
void rcc_set_adcpre(u32 adcpre);
|
||||
void rcc_set_ppre2(u32 ppre2);
|
||||
void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_usbpre(u32 usbpre);
|
||||
u32 rcc_get_system_clock_source(int i);
|
||||
void rcc_clock_setup_in_hsi_out_64mhz(void);
|
||||
void rcc_clock_setup_in_hsi_out_48mhz(void);
|
||||
|
||||
/**
|
||||
* Maximum speed possible for F100 (Value Line) on HSI
|
||||
*/
|
||||
void rcc_clock_setup_in_hsi_out_24mhz(void);
|
||||
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
|
||||
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
|
||||
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
|
||||
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
|
||||
void rcc_backupdomain_reset(void);
|
||||
|
||||
#endif
|
||||
@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
||||
-ffunction-sections -fdata-sections -MD -DSTM32L1
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = vector.o desig.o crc.o
|
||||
OBJS = vector.o desig.o crc.o gpio.o
|
||||
|
||||
VPATH += ../../usb:../
|
||||
|
||||
|
||||
84
lib/stm32/l1/libopencm3_stm32l1.ld
Normal file
84
lib/stm32/l1/libopencm3_stm32l1.ld
Normal file
@ -0,0 +1,84 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Generic linker script for STM32 targets using libopencm3. */
|
||||
|
||||
/* Memory regions must be defined in the ld script which includes this one. */
|
||||
|
||||
/* Enforce emmition of the vector table. */
|
||||
EXTERN (vector_table)
|
||||
|
||||
/* Define the entry point of the output file. */
|
||||
ENTRY(reset_handler)
|
||||
|
||||
/* Define sections. */
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(rom);
|
||||
|
||||
.text : {
|
||||
*(.vectors) /* Vector table */
|
||||
*(.text*) /* Program code */
|
||||
. = ALIGN(4);
|
||||
*(.rodata*) /* Read-only data */
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} >rom
|
||||
|
||||
/*
|
||||
* Another section used by C++ stuff, appears when using newlib with
|
||||
* 64bit (long long) printf support
|
||||
*/
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} >rom
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >rom
|
||||
|
||||
. = ORIGIN(ram);
|
||||
|
||||
.data : AT (__exidx_end) {
|
||||
_data = .;
|
||||
*(.data*) /* Read-write initialized data */
|
||||
. = ALIGN(4);
|
||||
_edata = .;
|
||||
} >ram
|
||||
|
||||
.bss : {
|
||||
*(.bss*) /* Read-write zero initialized data */
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
} >ram AT >rom
|
||||
|
||||
/*
|
||||
* The .eh_frame section appears to be used for C++ exception handling.
|
||||
* You may need to fix this if you're using C++.
|
||||
*/
|
||||
/DISCARD/ : { *(.eh_frame) }
|
||||
|
||||
. = ALIGN(4);
|
||||
end = .;
|
||||
}
|
||||
|
||||
PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
|
||||
|
||||
31
lib/stm32/l1/stm32l15xx8.ld
Normal file
31
lib/stm32/l1/stm32l15xx8.ld
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Linker script for STM32L15xx8, 64K flash, 10K RAM. */
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Include the common ld script. */
|
||||
INCLUDE libopencm3_stm32l1.ld
|
||||
|
||||
31
lib/stm32/l1/stm32l15xxB.ld
Normal file
31
lib/stm32/l1/stm32l15xxB.ld
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Linker script for STM32L15xxB, 128K flash, 16K RAM. */
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
/* Include the common ld script. */
|
||||
INCLUDE libopencm3_stm32l1.ld
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user