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stm32l0:rcc: add rcc_set_pll_source() as per L1

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reported by: kaeipnos in https://github.com/libopencm3/libopencm3/pull/609
This commit is contained in:
Karl Palsson 2018-02-24 13:42:20 +00:00
parent 28aa1e57e9
commit 8feb711ca0
2 changed files with 14 additions and 0 deletions
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1
include/libopencm3/stm32/l0/rcc.h
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@ -687,6 +687,7 @@ void rcc_set_hsi48_source_pll(void);
void rcc_set_sysclk_source(enum rcc_osc osc); void rcc_set_sysclk_source(enum rcc_osc osc);
void rcc_set_pll_multiplier(uint32_t factor); void rcc_set_pll_multiplier(uint32_t factor);
void rcc_set_pll_divider(uint32_t factor); void rcc_set_pll_divider(uint32_t factor);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1); void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre); void rcc_set_hpre(uint32_t hpre);

13
lib/stm32/l0/rcc.c
View File

@ -336,6 +336,19 @@ void rcc_set_pll_divider(uint32_t factor)
RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT); RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
} }
/**
* Set the pll source.
* @param pllsrc RCC_CFGR_PLLSRC_HSI16_CLK or RCC_CFGR_PLLSRC_HSE_CLK
*/
void rcc_set_pll_source(uint32_t pllsrc)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PLLSRC_HSE_CLK << 16);
RCC_CFGR = (reg32 | (pllsrc<<16));
}
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief RCC Set the APB1 Prescale Factor. /** @brief RCC Set the APB1 Prescale Factor.
* *