Cosmetic fixes.
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@ -688,6 +688,7 @@
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/* MA[31:0]: Memory address */
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/* --- Generic values ------------------------------------------------------ */
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#define DMA_CHANNEL1 1
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#define DMA_CHANNEL2 2
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#define DMA_CHANNEL3 3
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@ -64,6 +64,7 @@
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M3 System Interrupts */
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#define NVIC_NMI_IRQ -14
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#define NVIC_HARD_FAULT_IRQ -13
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@ -75,6 +75,7 @@
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/* --- SCB values ---------------------------------------------------------- */
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/* --- SCB_CPUID values ---------------------------------------------------- */
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/* Implementer[31:24]: Implementer code */
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#define SCP_CPUID_IMPLEMENTER_LSB 24
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/* Variant[23:20]: Variant number */
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@ -87,6 +88,7 @@
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#define SCP_CPUID_REVISION_LSB 0
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/* --- SCB_ICSR values ----------------------------------------------------- */
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/* NMIPENDSET: NMI set-pending bit */
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#define SCB_ICSR_NMIPENDSET (1 << 31)
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/* Bits [30:29]: reserved - must be kept cleared */
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@ -111,11 +113,13 @@
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#define SCB_ICSR_VECTACTIVE_LSB 0
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/* --- SCB_VTOR values ----------------------------------------------------- */
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/* Bits [31:30]: reserved - must be kept cleared */
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/* TBLOFF[29:9]: Vector table base offset field */
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#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
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/* --- SCB_AIRCR values ---------------------------------------------------- */
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/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
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#define SCB_AIRCR_VECTKEYSTAT_LSB 16
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/* ENDIANESS Data endianness bit */
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@ -137,6 +141,7 @@
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#define SCB_AIRCR_VECTRESET (1 << 0)
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/* --- SCB_SCR values ------------------------------------------------------ */
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/* Bits [31:5]: reserved - must be kept cleared */
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/* SEVEONPEND Send Event on Pending bit */
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#define SCB_SCR_SEVEONPEND (1 << 4)
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@ -148,6 +153,7 @@
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/* Bit 0: reserved - must be kept cleared */
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/* --- SCB_CCR values ------------------------------------------------------ */
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/* Bits [31:10]: reserved - must be kept cleared */
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/* STKALIGN */
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#define SCB_CCR_STKALIGN (1 << 9)
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@ -165,6 +171,7 @@
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#define SCB_CCR_NONBASETHRDENA (1 << 0)
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/* --- SCB_SHPR1 values ---------------------------------------------------- */
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/* Bits [31:24]: reserved - must be kept cleared */
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/* PRI_6[23:16]: Priority of system handler 6, usage fault */
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#define SCB_SHPR1_PRI_6_LSB 16
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@ -174,11 +181,13 @@
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#define SCB_SHPR1_PRI_4_LSB 0
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/* --- SCB_SHPR2 values ---------------------------------------------------- */
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/* PRI_11[31:24]: Priority of system handler 11, SVCall */
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#define SCB_SHPR2_PRI_11_LSB 24
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/* Bits [23:0]: reserved - must be kept cleared */
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/* --- SCB_SHPR3 values ---------------------------------------------------- */
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/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
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#define SCB_SHPR3_PRI_15_LSB 24
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/* PRI_14[23:16]: Priority of system handler 14, PendSV */
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@ -186,6 +195,7 @@
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/* Bits [15:0]: reserved - must be kept cleared */
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/* --- SCB_SHCSR values ---------------------------------------------------- */
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/* Bits [31:19]: reserved - must be kept cleared */
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/* USGFAULTENA: Usage fault enable */
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#define SCB_SHCSR_USGFAULTENA (1 << 18)
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@ -220,6 +230,7 @@
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#define SCB_SHCSR_MEMFAULTACT (1 << 0)
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/* --- SCB_CFSR values ----------------------------------------------------- */
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/* Bits [31:26]: reserved - must be kept cleared */
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/* DIVBYZERO: Divide by zero usage fault */
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#define SCB_CFSR_DIVBYZERO (1 << 25)
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@ -261,6 +272,7 @@
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#define SCB_CFSR_IACCVIOL (1 << 0)
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/* --- SCB_HFSR values ----------------------------------------------------- */
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/* DEBUG_VT: reserved for debug use */
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#define SCB_HFSR_DEBUG_VT (1 << 31)
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/* FORCED: Forced hard fault */
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@ -271,12 +283,15 @@
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/* Bit 0: reserved - must be kept cleared */
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/* --- SCB_MMFAR values ---------------------------------------------------- */
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/* MMFAR [31:0]: Memory management fault address */
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/* --- SCB_BFAR values ----------------------------------------------------- */
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/* BFAR [31:0]: Bus fault address */
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/* --- SCB functions ------------------------------------------------------- */
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/* TODO: */
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#endif
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