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Make more things static.

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No functional change intendend.
This commit is contained in:
Uwe Bonnes 2020-03-08 21:43:59 +01:00 committed by UweBonnes
parent eca3a8dd8f
commit a0e42e229b
7 changed files with 13 additions and 15 deletions
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4
src/target/adiv5.c
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@ -216,7 +216,7 @@ static const struct {
extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base); extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
void adiv5_dp_ref(ADIv5_DP_t *dp) static void adiv5_dp_ref(ADIv5_DP_t *dp)
{ {
dp->refcnt++; dp->refcnt++;
} }
@ -226,7 +226,7 @@ void adiv5_ap_ref(ADIv5_AP_t *ap)
ap->refcnt++; ap->refcnt++;
} }
void adiv5_dp_unref(ADIv5_DP_t *dp) static void adiv5_dp_unref(ADIv5_DP_t *dp)
{ {
if (--(dp->refcnt) == 0) if (--(dp->refcnt) == 0)
free(dp); free(dp);

2
src/target/adiv5.h
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@ -186,9 +186,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp);
void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel); ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel);
void adiv5_dp_ref(ADIv5_DP_t *dp);
void adiv5_ap_ref(ADIv5_AP_t *ap); void adiv5_ap_ref(ADIv5_AP_t *ap);
void adiv5_dp_unref(ADIv5_DP_t *dp);
void adiv5_ap_unref(ADIv5_AP_t *ap); void adiv5_ap_unref(ADIv5_AP_t *ap);
void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value); void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);

13
src/target/cortexm.c
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@ -53,11 +53,12 @@ const struct command_s cortexm_cmd_list[] = {
static void cortexm_regs_read(target *t, void *data); static void cortexm_regs_read(target *t, void *data);
static void cortexm_regs_write(target *t, const void *data); static void cortexm_regs_write(target *t, const void *data);
static uint32_t cortexm_pc_read(target *t); static uint32_t cortexm_pc_read(target *t);
ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max); static ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max);
ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max); static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max);
static void cortexm_reset(target *t); static void cortexm_reset(target *t);
static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch); static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch);
static void cortexm_halt_resume(target *t, bool step);
static void cortexm_halt_request(target *t); static void cortexm_halt_request(target *t);
static int cortexm_fault_unwind(target *t); static int cortexm_fault_unwind(target *t);
@ -549,7 +550,7 @@ int cortexm_mem_write_sized(
return target_check_error(t); return target_check_error(t);
} }
int dcrsr_regnum(target *t, unsigned reg) static int dcrsr_regnum(target *t, unsigned reg)
{ {
if (reg < sizeof(regnum_cortex_m) / 4) { if (reg < sizeof(regnum_cortex_m) / 4) {
return regnum_cortex_m[reg]; return regnum_cortex_m[reg];
@ -561,7 +562,7 @@ int dcrsr_regnum(target *t, unsigned reg)
return -1; return -1;
} }
} }
ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max) static ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
{ {
if (max < 4) if (max < 4)
return -1; return -1;
@ -571,7 +572,7 @@ ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
return 4; return 4;
} }
ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max) static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max)
{ {
if (max < 4) if (max < 4)
return -1; return -1;
@ -713,7 +714,7 @@ static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch)
return TARGET_HALT_BREAKPOINT; return TARGET_HALT_BREAKPOINT;
} }
void cortexm_halt_resume(target *t, bool step) static void cortexm_halt_resume(target *t, bool step)
{ {
struct cortexm_priv *priv = t->priv; struct cortexm_priv *priv = t->priv;
uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN; uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;

1
src/target/cortexm.h
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@ -175,7 +175,6 @@ ADIv5_AP_t *cortexm_ap(target *t);
bool cortexm_attach(target *t); bool cortexm_attach(target *t);
void cortexm_detach(target *t); void cortexm_detach(target *t);
void cortexm_halt_resume(target *t, bool step);
int cortexm_run_stub(target *t, uint32_t loadaddr, int cortexm_run_stub(target *t, uint32_t loadaddr,
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3); uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
int cortexm_mem_write_sized( int cortexm_mem_write_sized(

4
src/target/lmi.c
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@ -104,7 +104,7 @@ bool lmi_probe(target *t)
return false; return false;
} }
int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len) static int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
{ {
target *t = f->t; target *t = f->t;
@ -128,7 +128,7 @@ int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
return 0; return 0;
} }
int lmi_flash_write(struct target_flash *f, static int lmi_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len) target_addr dest, const void *src, size_t len)
{ {
target *t = f->t; target *t = f->t;

2
src/target/samd.c
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@ -329,7 +329,7 @@ samd20_revB_detach(target *t)
static void static void
samd20_revB_halt_resume(target *t, bool step) samd20_revB_halt_resume(target *t, bool step)
{ {
cortexm_halt_resume(t, step); target_halt_resume(t, step);
/* ---- Additional ---- */ /* ---- Additional ---- */
/* Exit extended reset */ /* Exit extended reset */

2
src/target/stm32f4.c
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@ -518,7 +518,7 @@ static bool stm32f4_cmd_erase_mass(target *t, int argc, const char **argv)
* * Documentation for F413 with OPTCR default = 0ffffffed seems wrong! * * Documentation for F413 with OPTCR default = 0ffffffed seems wrong!
*/ */
bool optcr_mask(target *t, uint32_t *val) static bool optcr_mask(target *t, uint32_t *val)
{ {
switch (t->idcode) { switch (t->idcode) {
case ID_STM32F20X: case ID_STM32F20X: