Cosmetic fixes.
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@ -2,7 +2,7 @@
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* This file is part of the libopenstm32 project.
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* This file is part of the libopenstm32 project.
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*
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>,
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>,
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* 2010 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -152,7 +152,6 @@
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#define GPIO_ETH_RXD2 GPIO0 /* PB0 */
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#define GPIO_ETH_RXD2 GPIO0 /* PB0 */
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#define GPIO_ETH_RXD3 GPIO1 /* PB1 */
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#define GPIO_ETH_RXD3 GPIO1 /* PB1 */
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/* --- GPIO registers ------------------------------------------------------ */
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/* --- GPIO registers ------------------------------------------------------ */
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/* Port configuration register low (GPIOx_CRL) */
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/* Port configuration register low (GPIOx_CRL) */
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@ -24,6 +24,7 @@
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#include <libopenstm32/common.h>
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#include <libopenstm32/common.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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@ -107,6 +108,7 @@
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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/* --- NVIC functions ------------------------------------------------------ */
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/* --- NVIC functions ------------------------------------------------------ */
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void nvic_enable_irq(s32 irqn);
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void nvic_enable_irq(s32 irqn);
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void nvic_disable_irq(s32 irqn);
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void nvic_disable_irq(s32 irqn);
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s32 nvic_get_pending_irq(s32 irqn);
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s32 nvic_get_pending_irq(s32 irqn);
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@ -20,20 +20,24 @@
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#ifndef LIBOPENSTM32_TOOLS_H
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#ifndef LIBOPENSTM32_TOOLS_H
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#define LIBOPENSTM32_TOOLS_H
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#define LIBOPENSTM32_TOOLS_H
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/******************************************************************************
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/*
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* Register accessors / manipulators
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* Register accessors / manipulators
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******************************************************************************/
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*/
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/* Get register content */
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/* Get register content. */
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#define GET_REG(REG) ((u16) *REG)
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#define GET_REG(REG) ((u16) *REG)
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/* Set register content */
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/* Set register content. */
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#define SET_REG(REG, VAL) (*REG = (u16)VAL)
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#define SET_REG(REG, VAL) (*REG = (u16)VAL)
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/* Clear register bit */
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/* Clear register bit. */
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#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
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#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
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/* Clear register bit masking out some bits that must not be touched */
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#define CLR_REG_BIT_MSK(REG, MSK, BIT) SET_REG(REG, (GET_REG(REG) & \
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/* Clear register bit masking out some bits that must not be touched. */
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MSK & (~BIT)))
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#define CLR_REG_BIT_MSK(REG, MSK, BIT) \
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/* Get masked out bit value */
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SET_REG(REG, (GET_REG(REG) & MSK & (~BIT)))
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/* Get masked out bit value. */
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#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT)
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#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT)
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/*
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/*
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@ -44,15 +48,17 @@
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* bitmask BIT then we write 1 and if the bit in the masked window is
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* bitmask BIT then we write 1 and if the bit in the masked window is
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* matching the bitmask BIT we write 0.
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* matching the bitmask BIT we write 0.
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*
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*
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* TODO: we may need a faster implementation of that one?
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* TODO: We may need a faster implementation of that one?
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*/
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*/
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#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) { \
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#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \
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register u16 toggle_mask = GET_REG(REG) & MSK; \
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{ \
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register u16 bit_selector; \
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register u16 toggle_mask = GET_REG(REG) & MSK; \
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for(bit_selector = 1; bit_selector; bit_selector <<= 1){ \
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register u16 bit_selector; \
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if((bit_selector & BIT) != 0) toggle_mask ^= bit_selector; \
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for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \
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} \
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if ((bit_selector & BIT) != 0) \
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SET_REG(REG, toggle_mask); \
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toggle_mask ^= bit_selector; \
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}
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} \
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SET_REG(REG, toggle_mask); \
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}
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#endif
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#endif
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@ -75,4 +75,3 @@ void rtc_disable_alarm(void)
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RTC_CRH &= ~RTC_CRH_ALRIE;
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RTC_CRH &= ~RTC_CRH_ALRIE;
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rtc_exit_config_mode();
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rtc_exit_config_mode();
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}
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}
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@ -98,4 +98,3 @@ u16 usart_recv(u32 usart)
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/* Receive data. */
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/* Receive data. */
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return USART_DR(usart) & 0x1ff;
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return USART_DR(usart) & 0x1ff;
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}
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}
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