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stm32f3: rcc: add hse preconfigurations

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Just a single 8Mhz in, 72mhz (max) out, which suits the f3 discovery
boards for instance.
This commit is contained in:
Karl Palsson 2018-05-04 21:28:11 +00:00
parent ee8b5bf4ac
commit ab9e425272
2 changed files with 28 additions and 6 deletions
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16
include/libopencm3/stm32/f3/rcc.h
View File

@ -413,11 +413,16 @@ extern uint32_t rcc_apb2_frequency;
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
enum rcc_clock { enum rcc_clock_hsi {
RCC_CLOCK_48MHZ, RCC_CLOCK_HSI_48MHZ,
RCC_CLOCK_64MHZ, RCC_CLOCK_HSI_64MHZ, /* Max from HSI */
RCC_CLOCK_END RCC_CLOCK_HSI_END
}; };
enum rcc_clock_hse8 {
RCC_CLOCK_HSE8_72MHZ,
RCC_CLOCK_HSE8_END
};
struct rcc_clock_scale { struct rcc_clock_scale {
uint8_t pllsrc; uint8_t pllsrc;
@ -434,7 +439,8 @@ struct rcc_clock_scale {
uint32_t apb2_frequency; uint32_t apb2_frequency;
}; };
extern const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END]; extern const struct rcc_clock_scale rcc_configs[RCC_CLOCK_HSI_END];
extern const struct rcc_clock_scale rcc_hse8mhz_configs[RCC_CLOCK_HSE8_END];
enum rcc_osc { enum rcc_osc {
RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI

18
lib/stm32/f3/rcc.c
View File

@ -44,7 +44,7 @@ uint32_t rcc_ahb_frequency = 8000000;
uint32_t rcc_apb1_frequency = 8000000; uint32_t rcc_apb1_frequency = 8000000;
uint32_t rcc_apb2_frequency = 8000000; uint32_t rcc_apb2_frequency = 8000000;
const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = { const struct rcc_clock_scale rcc_hsi_configs[] = {
{ /* 48MHz */ { /* 48MHz */
.pllmul = RCC_CFGR_PLLMUL_MUL12, .pllmul = RCC_CFGR_PLLMUL_MUL12,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
@ -69,6 +69,22 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
} }
}; };
const struct rcc_clock_scale rcc_hse8mhz_configs[] = {
{
.pllsrc = RCC_CFGR_PLLSRC_HSE_PREDIV,
.pllmul = RCC_CFGR_PLLMUL_MUL9,
.plldiv = RCC_CFGR2_PREDIV_NODIV,
.usbdiv1 = false,
.flash_waitstates = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.ahb_frequency = 72e6,
.apb1_frequency = 32e6,
.apb2_frequency = 72e6,
}
};
void rcc_osc_ready_int_clear(enum rcc_osc osc) void rcc_osc_ready_int_clear(enum rcc_osc osc)
{ {
switch (osc) { switch (osc) {