stm32f7: pwr: add more doxygen
Seeing as Matthew went to the effort of all the descriptions, it seemed only reasonable to get them to show up in the generated docs too.
This commit is contained in:
Karl Palsson
parent
17553da946
commit
ba0c97bf42
@ -28,6 +28,7 @@ EXCLUDE_PATTERNS = *_common_f*3.h *_common_f*3.c \
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*_common_*f013.h *_common_*f013.c \
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*_common_*f01.h *_common_*f01.c \ \
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*_common_*f03.h *_common_*f03.c
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EXCLUDE_PATTERNS += pwr_common_v1.* pwr_common_v2.*
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LAYOUT_FILE = DoxygenLayout_stm32f7.xml
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@ -36,25 +36,29 @@ LGPL License Terms @ref lgpl_license
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/**@{*/
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/* --- PWR registers ------------------------------------------------------- */
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/* Power control register (PWR_CR1) */
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/** @defgroup pwr_registers PWR Registers
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* @ingroup STM32F_pwr_defines
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@{*/
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/** Power control register (PWR_CR1) */
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#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
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/* Power control/status register (PWR_CSR1) */
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/** Power control/status register (PWR_CSR1) */
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#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04)
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/* Power control register 2 (PWR_CR2) */
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/** Power control register 2 (PWR_CR2) */
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#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08)
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/* Power control/status register 2 (PWR_CSR2) */
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/** Power control/status register 2 (PWR_CSR2) */
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#define PWR_CSR2 MMIO32(POWER_CONTROL_BASE + 0x0c)
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/*@}*/
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/* --- PWR_CR1 values ------------------------------------------------------- */
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/** @defgroup pwr_cr1_defines PWR_CR1 values
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* @ingroup STM32F_pwr_defines
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@{*/
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/* Bits [31:20]: Reserved, must be kept at reset value. */
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/* UDEN[19:18]: Under-drive enable in stop mode */
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/** UDEN[19:18]: Under-drive enable in stop mode */
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#define PWR_CR1_UDEN_LSB 18
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/** @defgroup pwr_uden Under-drive enable in stop mode
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@ingroup STM32F_pwr_defines
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@ -65,10 +69,10 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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#define PWR_CR1_UDEN_MASK (0x3 << PWR_CR1_UDEN_LSB)
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/* ODSWEN: Over-drive switching enabled */
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/** ODSWEN: Over-drive switching enabled */
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#define PWR_CR1_ODSWEN (1 << 17)
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/* ODEN: Over-drive enable */
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/** ODEN: Over-drive enable */
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#define PWR_CR1_ODEN (1 << 16)
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/* VOS[15:14]: Regulator voltage scaling output selection */
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@ -83,21 +87,21 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_LSB)
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/* ADCDC1: Masks extra flash accesses by prefetch (see AN4073) */
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/** ADCDC1: Masks extra flash accesses by prefetch (see AN4073) */
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#define PWR_CR1_ADCDC1 (1 << 13)
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/* Bit 12: Reserved, must be kept at reset value. */
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/* MRUDS: Main regulator in deepsleep under-drive mode */
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/** MRUDS: Main regulator in deepsleep under-drive mode */
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#define PWR_CR1_MRUDS (1 << 11)
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/* LPUDS: Low-power regulator in deepsleep under-drive mode */
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/** LPUDS: Low-power regulator in deepsleep under-drive mode */
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#define PWR_CR1_LPUDS (1 << 10)
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/* FPDS: Flash power-down in Stop mode */
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/** FPDS: Flash power-down in Stop mode */
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#define PWR_CR1_FPDS (1 << 9)
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/* DBP: Disable backup domain write protection */
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/** DBP: Disable backup domain write protection */
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#define PWR_CR1_DBP (1 << 8)
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/* PLS[7:5]: PVD level selection */
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@ -117,21 +121,24 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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#define PWR_CR1_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
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/* PVDE: Power voltage detector enable */
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/** PVDE: Power voltage detector enable */
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#define PWR_CR1_PVDE (1 << 4)
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/* CSBF: Clear standby flag */
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/** CSBF: Clear standby flag */
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#define PWR_CR1_CSBF (1 << 3)
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/* Bit 2: Reserved, must be kept at reset value. */
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/* PDDS: Power down deepsleep */
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/** PDDS: Power down deepsleep */
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#define PWR_CR1_PDDS (1 << 1)
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/* LPDS: Low-power deepsleep */
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/** LPDS: Low-power deepsleep */
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#define PWR_CR1_LPDS (1 << 0)
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/*@}*/
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/* --- PWR_CSR1 values ------------------------------------------------------ */
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/** @defgroup pwr_csr1_defines PWR_CSR1 values
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* @ingroup STM32F_pwr_defines
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@{*/
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/* Bits [31:20]: Reserved, must be kept at reset value. */
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@ -146,123 +153,129 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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#define PWR_CSR1_UDRDY_MASK (0x3 << PWR_CSR1_UDRDY_LSB)
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/* ODSWRDY: Over-drive mode switching ready */
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/** ODSWRDY: Over-drive mode switching ready */
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#define PWR_CSR1_ODSWRDY (1 << 17)
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/* ODRDY: Over-drive mode ready */
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/** ODRDY: Over-drive mode ready */
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#define PWR_CSR1_ODRDY (1 << 16)
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/* Bit 15: Reserved, must be kept at reset value. */
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/* VOSRDY: Regulator voltage scaling output selection ready bit */
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/** VOSRDY: Regulator voltage scaling output selection ready bit */
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#define PWR_CSR1_VOSRDY (1 << 14)
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/* Bits [13:10]: Reserved, must be kept at reset value. */
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/* BRE: Backup regulator enable */
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/** BRE: Backup regulator enable */
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#define PWR_CSR1_BRE (1 << 9)
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/* EIWUP: Enable internal wakeup */
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/** EIWUP: Enable internal wakeup */
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#define PWR_CSR1_EIWUP (1 << 8)
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/* Bits [7:4]: Reserved, must be kept at reset value. */
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/* BRR: Backup regulator ready */
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/** BRR: Backup regulator ready */
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#define PWR_CSR1_BRR (1 << 3)
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/* PVDO: PVD output */
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/** PVDO: PVD output */
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#define PWR_CSR1_PVDO (1 << 2)
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/* SBF: Standby flag */
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/** SBF: Standby flag */
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#define PWR_CSR1_SBF (1 << 1)
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/* WUIF: Wakeup internal flag */
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/** WUIF: Wakeup internal flag */
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#define PWR_CSR1_WUIF (1 << 0)
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/*@}*/
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/* --- PWR_CR2 values ------------------------------------------------------ */
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/** @defgroup pwr_cr2_defines PWR_CR2 values
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* @ingroup STM32F_pwr_defines
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@{*/
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/* Bits [31:14]: Reserved, must be kept at reset value. */
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/* WUPP6: Wakeup pin polarity bit for PI11 */
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/** WUPP6: Wakeup pin polarity bit for PI11 */
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#define PWR_CR2_WUPP6 (1 << 13)
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/* WUPP5: Wakeup pin polarity bit for PI8 */
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/** WUPP5: Wakeup pin polarity bit for PI8 */
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#define PWR_CR2_WUPP5 (1 << 12)
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/* WUPP4: Wakeup pin polarity bit for PC13 */
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/** WUPP4: Wakeup pin polarity bit for PC13 */
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#define PWR_CR2_WUPP4 (1 << 11)
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/* WUPP3: Wakeup pin polarity bit for PC1 */
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/** WUPP3: Wakeup pin polarity bit for PC1 */
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#define PWR_CR2_WUPP3 (1 << 10)
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/* WUPP2: Wakeup pin polarity bit for PA2 */
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/** WUPP2: Wakeup pin polarity bit for PA2 */
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#define PWR_CR2_WUPP2 (1 << 9)
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/* WUPP1: Wakeup pin polarity bit for PA0 */
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/** WUPP1: Wakeup pin polarity bit for PA0 */
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#define PWR_CR2_WUPP1 (1 << 8)
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/* Bits [7:6]: Reserved, must be kept at reset value. */
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/* CWUPF6: Clear Wakeup Pin flag for PI11 */
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/** CWUPF6: Clear Wakeup Pin flag for PI11 */
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#define PWR_CR2_CWUPF6 (1 << 5)
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/* CWUPF5: Clear Wakeup Pin flag for PI8 */
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/** CWUPF5: Clear Wakeup Pin flag for PI8 */
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#define PWR_CR2_CWUPF5 (1 << 4)
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/* CWUPF4: Clear Wakeup Pin flag for PC13 */
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/** CWUPF4: Clear Wakeup Pin flag for PC13 */
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#define PWR_CR2_CWUPF4 (1 << 3)
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/* CWUPF3: Clear Wakeup Pin flag for PC1 */
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/** CWUPF3: Clear Wakeup Pin flag for PC1 */
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#define PWR_CR2_CWUPF3 (1 << 2)
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/* CWUPF2: Clear Wakeup Pin flag for PA2 */
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/** CWUPF2: Clear Wakeup Pin flag for PA2 */
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#define PWR_CR2_CWUPF2 (1 << 1)
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/* CWUPF1: Clear Wakeup Pin flag for PA0 */
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/** CWUPF1: Clear Wakeup Pin flag for PA0 */
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#define PWR_CR2_CWUPF1 (1 << 0)
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/*@}*/
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/* --- PWR_CSR2 values ------------------------------------------------------ */
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/** @defgroup pwr_csr2_defines PWR_CSR2 values
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* @ingroup STM32F_pwr_defines
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@{*/
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/* Bits [31:14]: Reserved, must be kept at reset value. */
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/* EWUP6: Enable Wakeup pin for PI11 */
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/** EWUP6: Enable Wakeup pin for PI11 */
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#define PWR_CSR2_EWUP6 (1 << 13)
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/* EWUP5: Enable Wakeup pin for PI8 */
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/** EWUP5: Enable Wakeup pin for PI8 */
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#define PWR_CSR2_EWUP5 (1 << 12)
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/* EWUP4: Enable Wakeup pin for PC13 */
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/** EWUP4: Enable Wakeup pin for PC13 */
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#define PWR_CSR2_EWUP4 (1 << 11)
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/* EWUP3: Enable Wakeup pin for PC1 */
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/** EWUP3: Enable Wakeup pin for PC1 */
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#define PWR_CSR2_EWUP3 (1 << 10)
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/* EWUP2: Enable Wakeup pin for PA2 */
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/** EWUP2: Enable Wakeup pin for PA2 */
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#define PWR_CSR2_EWUP2 (1 << 19)
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/* EWUP1: Enable Wakeup pin for PA0 */
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/** EWUP1: Enable Wakeup pin for PA0 */
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#define PWR_CSR2_EWUP1 (1 << 18)
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/* Bits [7:6]: Reserved, must be kept at reset value. */
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/* WUPF6: Wakeup Pin flag for PI11 */
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/** WUPF6: Wakeup Pin flag for PI11 */
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#define PWR_CSR2_WUPF6 (1 << 5)
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/* WUPF5: Wakeup Pin flag for PI8 */
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/** WUPF5: Wakeup Pin flag for PI8 */
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#define PWR_CSR2_WUPF5 (1 << 4)
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/* WUPF4: Wakeup Pin flag for PC13 */
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/** WUPF4: Wakeup Pin flag for PC13 */
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#define PWR_CSR2_WUPF4 (1 << 3)
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/* WUPF3: Wakeup Pin flag for PC1 */
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/** WUPF3: Wakeup Pin flag for PC1 */
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#define PWR_CSR2_WUPF3 (1 << 2)
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/* WUPF2: Wakeup Pin flag for PA2 */
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/** WUPF2: Wakeup Pin flag for PA2 */
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#define PWR_CSR2_WUPF2 (1 << 1)
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/* WUPF1: Wakeup Pin flag for PA0 */
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/** WUPF1: Wakeup Pin flag for PA0 */
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#define PWR_CSR2_WUPF1 (1 << 0)
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/*@}*/
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/* --- Function prototypes ------------------------------------------------- */
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enum pwr_vos_scale {
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