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[eth/phy] Updated style

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This commit is contained in:
Frantisek Burian 2014-02-06 13:37:22 +01:00 committed by Karl Palsson
parent cbef4a15e4
commit c2c2ac766b
2 changed files with 59 additions and 24 deletions
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21
include/libopencm3/ethernet/mac_stm32fxx7.h
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@ -38,9 +38,16 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/**@{*/
/* Ethernet MAC registers */
#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00)
#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04)
#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08)
@ -115,6 +122,10 @@
#define ETH_DES6(base) ETH_DES(6, base)
#define ETH_DES7(base) ETH_DES(7, base)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/*---------------------------------------------------------------------------*/
/* MACCR --------------------------------------------------------------------*/
@ -697,6 +708,10 @@
#define ETH_RDES4_PFT (1<<12)
#define ETH_RDES4_PV (1<<13)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
enum eth_clk {
ETH_CLK_025_035MHZ = ETH_MACMIIAR_CR_HCLK_DIV_16,
ETH_CLK_035_060MHZ = ETH_MACMIIAR_CR_HCLK_DIV_26,
@ -705,6 +720,10 @@ enum eth_clk {
ETH_CLK_150_168MHZ = ETH_MACMIIAR_CR_HCLK_DIV_102,
};
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data);

18
include/libopencm3/ethernet/phy.h
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@ -37,7 +37,9 @@
/**@{*/
/* Registers */
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define PHY_REG_BCR 0x00
#define PHY_REG_BSR 0x01
@ -49,6 +51,10 @@
#define PHY_REG_ANNPTX 0x07
#define PHY_REG_ANNPRX 0x08
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
#define PHY_REG_BCR_COLTEST (1 << 7)
#define PHY_REG_BCR_FD (1 << 8)
#define PHY_REG_BCR_ANRST (1 << 9)
@ -64,6 +70,12 @@
#define PHY_REG_BSR_FAULT (1 << 4)
#define PHY_REG_BSR_ANDONE (1 << 5)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
#define PHY0 0
#define PHY1 1
@ -79,6 +91,10 @@ enum phy_status {
LINK_FD_10000M,
};
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void phy_reset(uint8_t phy);