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stm32f4: USB support for newer OTG cores

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Support for the  conflicting bit definitions for vbus sensing on core id
version 0x2000+

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
David Sidrane 2016-08-09 05:53:24 -10:00 committed by Karl Palsson
parent 6b5edeb091
commit cf80e2bd5e
2 changed files with 18 additions and 6 deletions
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6
include/libopencm3/stm32/otg_common.h
View File

@ -219,9 +219,11 @@
#define OTG_GRXSTSP_BCNT_MASK (0x7ff << 4) #define OTG_GRXSTSP_BCNT_MASK (0x7ff << 4)
#define OTG_GRXSTSP_EPNUM_MASK (0xf << 0) #define OTG_GRXSTSP_EPNUM_MASK (0xf << 0)
/* OTG general core configuration register (OTG_GCCFG) */
/* Bits 31:22 - Reserved */ /* Bits 31:22 - Reserved */
/** Only on cores < 0x2000 */
#define OTG_GCCFG_NOVBUSSENS (1 << 21) #define OTG_GCCFG_NOVBUSSENS (1 << 21)
/** Only on cores >= 0x2000 */
#define OTG_GCCFG_VBDEN (1 << 21)
#define OTG_GCCFG_SOFOUTEN (1 << 20) #define OTG_GCCFG_SOFOUTEN (1 << 20)
#define OTG_GCCFG_VBUSBSEN (1 << 19) #define OTG_GCCFG_VBUSBSEN (1 << 19)
#define OTG_GCCFG_VBUSASEN (1 << 18) #define OTG_GCCFG_VBUSASEN (1 << 18)
@ -229,6 +231,8 @@
#define OTG_GCCFG_PWRDWN (1 << 16) #define OTG_GCCFG_PWRDWN (1 << 16)
/* Bits 15:0 - Reserved */ /* Bits 15:0 - Reserved */
/* OTG FS Product ID register (OTG_CID) */
#define OTG_CID_HAS_VBDEN 0x00002000
/* Device-mode CSRs */ /* Device-mode CSRs */
/* OTG device control register (OTG_DCTL) */ /* OTG device control register (OTG_DCTL) */

16
lib/usb/usb_f107.c
View File

@ -54,11 +54,7 @@ const struct _usbd_driver stm32f107_usb_driver = {
static usbd_device *stm32f107_usbd_init(void) static usbd_device *stm32f107_usbd_init(void)
{ {
rcc_periph_clock_enable(RCC_OTGFS); rcc_periph_clock_enable(RCC_OTGFS);
OTG_FS_GINTSTS = OTG_GINTSTS_MMIS;
OTG_FS_GUSBCFG |= OTG_GUSBCFG_PHYSEL; OTG_FS_GUSBCFG |= OTG_GUSBCFG_PHYSEL;
/* Enable VBUS sensing in device mode and power down the PHY. */
OTG_FS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
/* Wait for AHB idle. */ /* Wait for AHB idle. */
while (!(OTG_FS_GRSTCTL & OTG_GRSTCTL_AHBIDL)); while (!(OTG_FS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
@ -66,9 +62,21 @@ static usbd_device *stm32f107_usbd_init(void)
OTG_FS_GRSTCTL |= OTG_GRSTCTL_CSRST; OTG_FS_GRSTCTL |= OTG_GRSTCTL_CSRST;
while (OTG_FS_GRSTCTL & OTG_GRSTCTL_CSRST); while (OTG_FS_GRSTCTL & OTG_GRSTCTL_CSRST);
if (OTG_FS_CID >= OTG_CID_HAS_VBDEN) {
/* Enable VBUS detection in device mode and power up the PHY. */
OTG_FS_GCCFG |= OTG_GCCFG_VBDEN | OTG_GCCFG_PWRDWN;
} else {
/* Enable VBUS sensing in device mode and power up the PHY. */
OTG_FS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
}
/* Explicitly enable DP pullup (not all cores do this by default) */
OTG_FS_DCTL &= ~OTG_DCTL_SDIS;
/* Force peripheral only mode. */ /* Force peripheral only mode. */
OTG_FS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK; OTG_FS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK;
OTG_FS_GINTSTS = OTG_GINTSTS_MMIS;
/* Full speed device. */ /* Full speed device. */
OTG_FS_DCFG |= OTG_DCFG_DSPD; OTG_FS_DCFG |= OTG_DCFG_DSPD;