stm32f4: USB support for newer OTG cores
Support for the conflicting bit definitions for vbus sensing on core id version 0x2000+ Reviewed-by: Karl Palsson <karlp@tweak.net.au>
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@ -219,9 +219,11 @@
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#define OTG_GRXSTSP_BCNT_MASK (0x7ff << 4)
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#define OTG_GRXSTSP_EPNUM_MASK (0xf << 0)
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/* OTG general core configuration register (OTG_GCCFG) */
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/* Bits 31:22 - Reserved */
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#define OTG_GCCFG_NOVBUSSENS (1 << 21)
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/** Only on cores < 0x2000 */
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#define OTG_GCCFG_NOVBUSSENS (1 << 21)
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/** Only on cores >= 0x2000 */
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#define OTG_GCCFG_VBDEN (1 << 21)
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#define OTG_GCCFG_SOFOUTEN (1 << 20)
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#define OTG_GCCFG_VBUSBSEN (1 << 19)
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#define OTG_GCCFG_VBUSASEN (1 << 18)
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@ -229,6 +231,8 @@
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#define OTG_GCCFG_PWRDWN (1 << 16)
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/* Bits 15:0 - Reserved */
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/* OTG FS Product ID register (OTG_CID) */
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#define OTG_CID_HAS_VBDEN 0x00002000
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/* Device-mode CSRs */
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/* OTG device control register (OTG_DCTL) */
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@ -54,11 +54,7 @@ const struct _usbd_driver stm32f107_usb_driver = {
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static usbd_device *stm32f107_usbd_init(void)
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{
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rcc_periph_clock_enable(RCC_OTGFS);
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OTG_FS_GINTSTS = OTG_GINTSTS_MMIS;
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OTG_FS_GUSBCFG |= OTG_GUSBCFG_PHYSEL;
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/* Enable VBUS sensing in device mode and power down the PHY. */
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OTG_FS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
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/* Wait for AHB idle. */
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while (!(OTG_FS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
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@ -66,9 +62,21 @@ static usbd_device *stm32f107_usbd_init(void)
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OTG_FS_GRSTCTL |= OTG_GRSTCTL_CSRST;
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while (OTG_FS_GRSTCTL & OTG_GRSTCTL_CSRST);
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if (OTG_FS_CID >= OTG_CID_HAS_VBDEN) {
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/* Enable VBUS detection in device mode and power up the PHY. */
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OTG_FS_GCCFG |= OTG_GCCFG_VBDEN | OTG_GCCFG_PWRDWN;
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} else {
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/* Enable VBUS sensing in device mode and power up the PHY. */
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OTG_FS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
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}
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/* Explicitly enable DP pullup (not all cores do this by default) */
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OTG_FS_DCTL &= ~OTG_DCTL_SDIS;
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/* Force peripheral only mode. */
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OTG_FS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK;
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OTG_FS_GINTSTS = OTG_GINTSTS_MMIS;
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/* Full speed device. */
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OTG_FS_DCFG |= OTG_DCFG_DSPD;
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