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adiv5: CMSIS DAP transactions are slow but work in principle

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Slowness results in strange STM32F767 DHCSR implementation to nearly never
halt in the given 2 second period when F767 is sleeping most of the time.
This commit is contained in:
Uwe Bonnes 2021-10-09 13:12:10 +02:00
parent 761e0230d4
commit d144f9d54b
1 changed files with 1 additions and 6 deletions
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7
src/target/adiv5.c
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@ -323,12 +323,7 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
CORTEXM_DHCSR_C_HALT; CORTEXM_DHCSR_C_HALT;
uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN; uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN;
bool reset_seen = false; bool reset_seen = false;
bool is_mindp = (ap->dp->idcode & ADIV5_MINDP); bool use_low_access = (!(ap->dp->idcode & ADIV5_MINDP));
#if PC_HOSTED == 1
bool use_low_access = (!(ap->dp->ap_setup) && !is_mindp);
#else
bool use_low_access = (!is_mindp);
#endif
if (use_low_access) { if (use_low_access) {
/* ap_mem_access_setup() sets ADIV5_AP_CSW_ADDRINC_SINGLE -> unusable!*/ /* ap_mem_access_setup() sets ADIV5_AP_CSW_ADDRINC_SINGLE -> unusable!*/
adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD); adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);