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[l1] PWR: fix style for common code

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Code added for L1 to support the PWR Control block didn't properly
follow the HACKING_COMMON_DOC guidelines.  The naming was wrong, and
some headers were missing.  This commit has no functional changes, it
only addresses the style and structure problems.
This commit is contained in:
Karl Palsson 2013-01-22 22:27:38 +00:00
parent 48eed286b9
commit df5e3e5ff1
12 changed files with 446 additions and 135 deletions
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119
include/libopencm3/stm32/common/pwr_common_all.h Normal file
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@ -0,0 +1,119 @@
/** @addtogroup pwr_defines */
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
#define LIBOPENCM3_PWR_COMMON_ALL_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- PWR registers ------------------------------------------------------- */
/* Power control register (PWR_CR) */
#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
/* Power control/status register (PWR_CSR) */
#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
/* --- PWR_CR values ------------------------------------------------------- */
/* Bits [31:9]: Reserved, must be kept at reset value. */
/* DBP: Disable backup domain write protection */
#define PWR_CR_DBP (1 << 8)
/* PLS[7:5]: PVD level selection */
#define PWR_CR_PLS_LSB 5
/** @defgroup pwr_pls PVD level selection
@ingroup STM32F_pwr_defines
@{*/
#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
/**@}*/
#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
/* PVDE: Power voltage detector enable */
#define PWR_CR_PVDE (1 << 4)
/* CSBF: Clear standby flag */
#define PWR_CR_CSBF (1 << 3)
/* CWUF: Clear wakeup flag */
#define PWR_CR_CWUF (1 << 2)
/* PDDS: Power down deepsleep */
#define PWR_CR_PDDS (1 << 1)
/* LPDS: Low-power deepsleep */
#define PWR_CR_LPDS (1 << 0)
/* --- PWR_CSR values ------------------------------------------------------ */
/* Bits [31:9]: Reserved, must be kept at reset value. */
/* EWUP: Enable WKUP pin */
#define PWR_CSR_EWUP (1 << 8)
/* Bits [7:3]: Reserved, must be kept at reset value. */
/* PVDO: PVD output */
#define PWR_CSR_PVDO (1 << 2)
/* SBF: Standby flag */
#define PWR_CSR_SBF (1 << 1)
/* WUF: Wakeup flag */
#define PWR_CSR_WUF (1 << 0)
/* --- PWR function prototypes ------------------------------------------- */
BEGIN_DECLS
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_power_voltage_detect(u32 pvd_level);
void pwr_disable_power_voltage_detect(void);
void pwr_clear_standby_flag(void);
void pwr_clear_wakeup_flag(void);
void pwr_set_standby_mode(void);
void pwr_set_stop_mode(void);
void pwr_voltage_regulator_on_in_stop(void);
void pwr_voltage_regulator_low_power_in_stop(void);
void pwr_enable_wakeup_pin(void);
void pwr_disable_wakeup_pin(void);
bool pwr_voltage_high(void);
bool pwr_get_standby_flag(void);
bool pwr_get_wakeup_flag(void);
END_DECLS
/**@}*/
#endif

40
include/libopencm3/stm32/f1/pwr.h Normal file
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@ -0,0 +1,40 @@
/** @defgroup pwr_defines PWR Defines
@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/pwr_common_all.h>
#endif

19
include/libopencm3/stm32/f4/pwr.h
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@ -1,3 +1,15 @@
/** @defgroup pwr_defines PWR Defines
@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b>
@ingroup STM32F4xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
@ -17,10 +29,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef LIBOPENCM3_PWR_F4_H #ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_F4_H #define LIBOPENCM3_PWR_H
#include <libopencm3/stm32/pwr.h> #include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/pwr_common_all.h>
/* /*
* This file extends the common STM32 version with definitions only * This file extends the common STM32 version with definitions only

53
include/libopencm3/stm32/l1/pwr.h
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@ -1,3 +1,18 @@
/** @defgroup pwr_defines PWR Defines
@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
@ingroup STM32L1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
@date 1 July 2012
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
@ -18,10 +33,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef LIBOPENCM3_PWR_L1_H #ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_L1_H #define LIBOPENCM3_PWR_H
#include <libopencm3/stm32/pwr.h> #include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/pwr_common_all.h>
/* /*
* This file extends the common STM32 version with definitions only * This file extends the common STM32 version with definitions only
@ -33,47 +49,52 @@
/* Bits [31:15]: Reserved */ /* Bits [31:15]: Reserved */
/* LPRUN: Low power run mode */ /* LPRUN: Low power run mode */
#define PWR_CR_LPRUN (1 << 14) #define PWR_CR_LPRUN (1 << 14)
/* VOS[12:11]: Regulator voltage scaling output selection */ /* VOS[12:11]: Regulator voltage scaling output selection */
#define PWR_CR_VOS_LSB 11 #define PWR_CR_VOS_LSB 11
/** @defgroup pwr_vos Voltage Scaling Output level selection /** @defgroup pwr_vos Voltage Scaling Output level selection
@ingroup STM32F_pwr_defines @ingroup STM32F_pwr_defines
@{*/ @{*/
#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) #define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB)
#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) #define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB)
#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) #define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB)
/**@}*/ /**@}*/
#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) #define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB)
/* FWU: Fast wakeup */ /* FWU: Fast wakeup */
#define PWR_CR_FWU (1 << 10) #define PWR_CR_FWU (1 << 10)
/* ULP: Ultralow power mode */ /* ULP: Ultralow power mode */
#define PWR_CR_ULP (1 << 9) #define PWR_CR_ULP (1 << 9)
/* LPSDSR: Low-power deepsleep/sleep/low power run */
#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
/* --- PWR_CSR values ------------------------------------------------------- */ /* --- PWR_CSR values ------------------------------------------------------- */
/* Bits [31:11]: Reserved */ /* Bits [31:11]: Reserved */
/* EWUP3: Enable WKUP3 pin */ /* EWUP3: Enable WKUP3 pin */
#define PWR_CSR_EWUP3 (1 << 10) #define PWR_CSR_EWUP3 (1 << 10)
/* EWUP2: Enable WKUP2 pin */ /* EWUP2: Enable WKUP2 pin */
#define PWR_CSR_EWUP2 (1 << 9) #define PWR_CSR_EWUP2 (1 << 9)
/* EWUP1: Enable WKUP1 pin */ /* EWUP1: Enable WKUP1 pin */
#define PWR_CSR_EWUP1 PWR_CSR_EWUP #define PWR_CSR_EWUP1 PWR_CSR_EWUP
/* REGLPF : Regulator LP flag */ /* REGLPF : Regulator LP flag */
#define PWR_CSR_REGLPF (1 << 5) #define PWR_CSR_REGLPF (1 << 5)
/* VOSF: Voltage Scaling select flag */ /* VOSF: Voltage Scaling select flag */
#define PWR_CSR_VOSF (1 << 4) #define PWR_CSR_VOSF (1 << 4)
/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ /* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */
#define PWR_CSR_VREFINTRDYF (1 << 3) #define PWR_CSR_VREFINTRDYF (1 << 3)
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
typedef enum { typedef enum {

2
include/libopencm3/stm32/l1/rcc.h
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@ -46,7 +46,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/memorymap.h> #include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h> #include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/l1/pwr.h> #include <libopencm3/stm32/pwr.h>
/* --- RCC registers ------------------------------------------------------- */ /* --- RCC registers ------------------------------------------------------- */

122
include/libopencm3/stm32/pwr.h
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@ -1,22 +1,8 @@
/** @defgroup STM32F_pwr_defines PWR Defines /* This provides unification of code over STM32F subfamilies */
@ingroup STM32F_defines
@brief <b>libopencm3 STM32F Power Control</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 17 August 2012
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify * This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by * it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or * the Free Software Foundation, either version 3 of the License, or
@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
/**@{*/ #if defined(STM32F1)
# include <libopencm3/stm32/f1/pwr.h>
#ifndef LIBOPENCM3_PWR_H #elif defined(STM32F2)
#define LIBOPENCM3_PWR_H # include <libopencm3/stm32/f2/pwr.h>
#elif defined(STM32F4)
#include <libopencm3/stm32/memorymap.h> # include <libopencm3/stm32/f4/pwr.h>
#include <libopencm3/cm3/common.h> #elif defined(STM32L1)
# include <libopencm3/stm32/l1/pwr.h>
/* --- PWR registers ------------------------------------------------------- */ #else
# error "stm32 family not defined."
/* Power control register (PWR_CR) */
#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
/* Power control/status register (PWR_CSR) */
#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
/* --- PWR_CR values ------------------------------------------------------- */
/* Bits [31:9]: Reserved, must be kept at reset value. */
/* DBP: Disable backup domain write protection */
#define PWR_CR_DBP (1 << 8)
/* PLS[7:5]: PVD level selection */
#define PWR_CR_PLS_LSB 5
/** @defgroup pwr_pls PVD level selection
@ingroup STM32F_pwr_defines
@{*/
#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
/**@}*/
#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
/* PVDE: Power voltage detector enable */
#define PWR_CR_PVDE (1 << 4)
/* CSBF: Clear standby flag */
#define PWR_CR_CSBF (1 << 3)
/* CWUF: Clear wakeup flag */
#define PWR_CR_CWUF (1 << 2)
/* PDDS: Power down deepsleep */
#define PWR_CR_PDDS (1 << 1)
/* LPDS: Low-power deepsleep */
#define PWR_CR_LPDS (1 << 0)
/* --- PWR_CSR values ------------------------------------------------------ */
/* Bits [31:9]: Reserved, must be kept at reset value. */
/* EWUP: Enable WKUP pin */
#define PWR_CSR_EWUP (1 << 8)
/* Bits [7:3]: Reserved, must be kept at reset value. */
/* PVDO: PVD output */
#define PWR_CSR_PVDO (1 << 2)
/* SBF: Standby flag */
#define PWR_CSR_SBF (1 << 1)
/* WUF: Wakeup flag */
#define PWR_CSR_WUF (1 << 0)
/* --- PWR function prototypes ------------------------------------------- */
BEGIN_DECLS
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_power_voltage_detect(u32 pvd_level);
void pwr_disable_power_voltage_detect(void);
void pwr_clear_standby_flag(void);
void pwr_clear_wakeup_flag(void);
void pwr_set_standby_mode(void);
void pwr_set_stop_mode(void);
void pwr_voltage_regulator_on_in_stop(void);
void pwr_voltage_regulator_low_power_in_stop(void);
void pwr_enable_wakeup_pin(void);
void pwr_disable_wakeup_pin(void);
bool pwr_voltage_high(void);
bool pwr_get_standby_flag(void);
bool pwr_get_wakeup_flag(void);
END_DECLS
#endif #endif
/**@}*/

217
lib/stm32/common/pwr_common_all.c Normal file
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@ -0,0 +1,217 @@
/** @defgroup STM32F1xx-pwr-file PWR
@ingroup STM32F1xx
@brief <b>libopencm3 STM32F1xx Power Control</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 18 August 2012
This library supports the power control system for the
STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/pwr.h>
/*---------------------------------------------------------------------------*/
/** @brief Disable Backup Domain Write Protection.
This allows backup domain registers to be changed. These registers are write
protected after a reset.
*/
void pwr_disable_backup_domain_write_protect(void)
{
PWR_CR |= PWR_CR_DBP;
}
/*---------------------------------------------------------------------------*/
/** @brief Re-enable Backup Domain Write Protection.
This protects backup domain registers from inadvertent change.
*/
void pwr_enable_backup_domain_write_protect(void)
{
PWR_CR &= ~PWR_CR_DBP;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable Power Voltage Detector.
This provides voltage level threshold detection. The result of detection is
provided in the power voltage detector output flag (see @ref pwr_voltage_high)
or by setting the EXTI16 interrupt (see datasheet for configuration details).
@param[in] pvd_level u32. Taken from @ref pwr_pls.
*/
void pwr_enable_power_voltage_detect(u32 pvd_level)
{
PWR_CR &= ~PWR_CR_PLS_MASK;
PWR_CR |= (PWR_CR_PVDE | pvd_level);
}
/*---------------------------------------------------------------------------*/
/** @brief Disable Power Voltage Detector.
*/
void pwr_disable_power_voltage_detect(void)
{
PWR_CR &= ~PWR_CR_PVDE;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Standby Flag.
This is set when the processor returns from a standby mode.
*/
void pwr_clear_standby_flag(void)
{
PWR_CR |= PWR_CR_CSBF;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Wakeup Flag.
This is set when the processor receives a wakeup signal.
*/
void pwr_clear_wakeup_flag(void)
{
PWR_CR |= PWR_CR_CWUF;
}
/*---------------------------------------------------------------------------*/
/** @brief Set Standby Mode in Deep Sleep.
*/
void pwr_set_standby_mode(void)
{
PWR_CR |= PWR_CR_PDDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Set Stop Mode in Deep Sleep.
*/
void pwr_set_stop_mode(void)
{
PWR_CR &= ~PWR_CR_PDDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Voltage Regulator On in Stop Mode.
*/
void pwr_voltage_regulator_on_in_stop(void)
{
PWR_CR &= ~PWR_CR_LPDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Voltage Regulator Low Power in Stop Mode.
*/
void pwr_voltage_regulator_low_power_in_stop(void)
{
PWR_CR |= PWR_CR_LPDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable Wakeup Pin.
The wakeup pin is used for waking the processor from standby mode.
*/
void pwr_enable_wakeup_pin(void)
{
PWR_CSR |= PWR_CSR_EWUP;
}
/*---------------------------------------------------------------------------*/
/** @brief Release Wakeup Pin.
The wakeup pin is used for general purpose I/O.
*/
void pwr_disable_wakeup_pin(void)
{
PWR_CSR &= ~PWR_CSR_EWUP;
}
/*---------------------------------------------------------------------------*/
/** @brief Get Voltage Detector Output.
The voltage detector threshold must be set when the power voltage detector is
enabled, see @ref pwr_enable_power_voltage_detect.
@returns boolean: TRUE if the power voltage is above the preset voltage
threshold.
*/
bool pwr_voltage_high(void)
{
return (PWR_CSR & PWR_CSR_PVDO);
}
/*---------------------------------------------------------------------------*/
/** @brief Get Standby Flag.
The standby flag is set when the processor returns from a standby state. It is
cleared by software (see @ref pwr_clear_standby_flag).
@returns boolean: TRUE if the processor was in standby state.
*/
bool pwr_get_standby_flag(void)
{
return (PWR_CSR & PWR_CSR_SBF);
}
/*---------------------------------------------------------------------------*/
/** @brief Get Wakeup Flag.
The wakeup flag is set when a wakeup event has been received. It is
cleared by software (see @ref pwr_clear_wakeup_flag).
@returns boolean: TRUE if a wakeup event was received.
*/
bool pwr_get_wakeup_flag(void)
{
return (PWR_CSR & PWR_CSR_WUF);
}
/**@}*/

2
lib/stm32/f1/Makefile
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@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
ARFLAGS = rcs ARFLAGS = rcs
OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \ OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \
timer.o usb_f107.o desig.o pwr.o \ timer.o usb_f107.o desig.o pwr_common_all.o \
usb_fx07_common.o \ usb_fx07_common.o \
gpio_common_all.o dma_common_f13.o spi_common_all.o \ gpio_common_all.o dma_common_f13.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o \ dac_common_all.o usart_common_all.o iwdg_common_all.o \

1
lib/stm32/f4/Makefile
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@ -32,6 +32,7 @@ ARFLAGS = rcs
OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \ OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
usb_f207.o adc.o dma.o \ usb_f207.o adc.o dma.o \
pwr_common_all.o \
gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \ gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \ dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
crc_common_all.o crc_common_all.o

2
lib/stm32/l1/Makefile
View File

@ -31,7 +31,7 @@ ARFLAGS = rcs
OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o
OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o
OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o
OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o OBJS += pwr_common_all.o pwr.o
VPATH += ../../usb:../:../../cm3:../common VPATH += ../../usb:../:../../cm3:../common

2
lib/stm32/l1/pwr_chipset.c → lib/stm32/l1/pwr.c
View File

@ -17,7 +17,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <libopencm3/stm32/l1/pwr.h> #include <libopencm3/stm32/pwr.h>
void pwr_set_vos_scale(vos_scale_t scale) void pwr_set_vos_scale(vos_scale_t scale)
{ {

2
lib/stm32/l1/rcc.c
View File

@ -23,7 +23,7 @@
#include <libopencm3/stm32/l1/rcc.h> #include <libopencm3/stm32/l1/rcc.h>
#include <libopencm3/stm32/l1/flash.h> #include <libopencm3/stm32/l1/flash.h>
#include <libopencm3/stm32/l1/pwr.h> #include <libopencm3/stm32/pwr.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 2097000; u32 rcc_ppre1_frequency = 2097000;