[l1] PWR: fix style for common code
Code added for L1 to support the PWR Control block didn't properly follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and some headers were missing. This commit has no functional changes, it only addresses the style and structure problems.
This commit is contained in:
Karl Palsson
parent
48eed286b9
commit
df5e3e5ff1
119
include/libopencm3/stm32/common/pwr_common_all.h
Normal file
119
include/libopencm3/stm32/common/pwr_common_all.h
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@ -0,0 +1,119 @@
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/** @addtogroup pwr_defines */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
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#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
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#define LIBOPENCM3_PWR_COMMON_ALL_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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/* --- PWR registers ------------------------------------------------------- */
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/* Power control register (PWR_CR) */
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#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
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/* Power control/status register (PWR_CSR) */
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#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
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/* --- PWR_CR values ------------------------------------------------------- */
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/* Bits [31:9]: Reserved, must be kept at reset value. */
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/* DBP: Disable backup domain write protection */
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#define PWR_CR_DBP (1 << 8)
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/* PLS[7:5]: PVD level selection */
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#define PWR_CR_PLS_LSB 5
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/** @defgroup pwr_pls PVD level selection
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
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/**@}*/
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#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
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/* PVDE: Power voltage detector enable */
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#define PWR_CR_PVDE (1 << 4)
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/* CSBF: Clear standby flag */
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#define PWR_CR_CSBF (1 << 3)
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/* CWUF: Clear wakeup flag */
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#define PWR_CR_CWUF (1 << 2)
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/* PDDS: Power down deepsleep */
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#define PWR_CR_PDDS (1 << 1)
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/* LPDS: Low-power deepsleep */
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#define PWR_CR_LPDS (1 << 0)
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/* --- PWR_CSR values ------------------------------------------------------ */
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/* Bits [31:9]: Reserved, must be kept at reset value. */
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/* EWUP: Enable WKUP pin */
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#define PWR_CSR_EWUP (1 << 8)
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/* Bits [7:3]: Reserved, must be kept at reset value. */
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/* PVDO: PVD output */
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#define PWR_CSR_PVDO (1 << 2)
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/* SBF: Standby flag */
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#define PWR_CSR_SBF (1 << 1)
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/* WUF: Wakeup flag */
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#define PWR_CSR_WUF (1 << 0)
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/* --- PWR function prototypes ------------------------------------------- */
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BEGIN_DECLS
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void pwr_disable_backup_domain_write_protect(void);
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void pwr_enable_backup_domain_write_protect(void);
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void pwr_enable_power_voltage_detect(u32 pvd_level);
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void pwr_disable_power_voltage_detect(void);
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void pwr_clear_standby_flag(void);
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void pwr_clear_wakeup_flag(void);
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void pwr_set_standby_mode(void);
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void pwr_set_stop_mode(void);
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void pwr_voltage_regulator_on_in_stop(void);
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void pwr_voltage_regulator_low_power_in_stop(void);
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void pwr_enable_wakeup_pin(void);
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void pwr_disable_wakeup_pin(void);
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bool pwr_voltage_high(void);
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bool pwr_get_standby_flag(void);
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bool pwr_get_wakeup_flag(void);
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END_DECLS
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/**@}*/
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#endif
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40
include/libopencm3/stm32/f1/pwr.h
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40
include/libopencm3/stm32/f1/pwr.h
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@ -0,0 +1,40 @@
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/** @defgroup pwr_defines PWR Defines
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@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
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@ingroup STM32F1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@date 5 December 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/pwr_common_all.h>
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#endif
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@ -1,3 +1,15 @@
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/** @defgroup pwr_defines PWR Defines
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@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b>
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@ingroup STM32F4xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@ -17,10 +29,11 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_F4_H
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#define LIBOPENCM3_PWR_F4_H
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/pwr_common_all.h>
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/*
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* This file extends the common STM32 version with definitions only
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@ -1,3 +1,18 @@
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/** @defgroup pwr_defines PWR Defines
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@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
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@ingroup STM32L1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
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@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
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@date 1 July 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@ -18,10 +33,11 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_L1_H
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#define LIBOPENCM3_PWR_L1_H
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/pwr_common_all.h>
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/*
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* This file extends the common STM32 version with definitions only
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@ -33,47 +49,52 @@
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/* Bits [31:15]: Reserved */
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/* LPRUN: Low power run mode */
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#define PWR_CR_LPRUN (1 << 14)
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#define PWR_CR_LPRUN (1 << 14)
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/* VOS[12:11]: Regulator voltage scaling output selection */
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#define PWR_CR_VOS_LSB 11
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#define PWR_CR_VOS_LSB 11
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/** @defgroup pwr_vos Voltage Scaling Output level selection
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB)
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/**@}*/
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#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB)
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/* FWU: Fast wakeup */
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#define PWR_CR_FWU (1 << 10)
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#define PWR_CR_FWU (1 << 10)
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/* ULP: Ultralow power mode */
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#define PWR_CR_ULP (1 << 9)
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#define PWR_CR_ULP (1 << 9)
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/* LPSDSR: Low-power deepsleep/sleep/low power run */
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#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
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/* --- PWR_CSR values ------------------------------------------------------- */
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/* Bits [31:11]: Reserved */
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/* EWUP3: Enable WKUP3 pin */
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#define PWR_CSR_EWUP3 (1 << 10)
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#define PWR_CSR_EWUP3 (1 << 10)
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/* EWUP2: Enable WKUP2 pin */
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#define PWR_CSR_EWUP2 (1 << 9)
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#define PWR_CSR_EWUP2 (1 << 9)
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/* EWUP1: Enable WKUP1 pin */
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#define PWR_CSR_EWUP1 PWR_CSR_EWUP
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#define PWR_CSR_EWUP1 PWR_CSR_EWUP
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/* REGLPF : Regulator LP flag */
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#define PWR_CSR_REGLPF (1 << 5)
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#define PWR_CSR_REGLPF (1 << 5)
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/* VOSF: Voltage Scaling select flag */
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#define PWR_CSR_VOSF (1 << 4)
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#define PWR_CSR_VOSF (1 << 4)
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/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */
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#define PWR_CSR_VREFINTRDYF (1 << 3)
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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@ -46,7 +46,7 @@ LGPL License Terms @ref lgpl_license
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/l1/pwr.h>
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#include <libopencm3/stm32/pwr.h>
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/* --- RCC registers ------------------------------------------------------- */
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@ -1,22 +1,8 @@
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/** @defgroup STM32F_pwr_defines PWR Defines
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/* This provides unification of code over STM32F subfamilies */
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@ingroup STM32F_defines
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@brief <b>libopencm3 STM32F Power Control</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@date 17 August 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- PWR registers ------------------------------------------------------- */
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/* Power control register (PWR_CR) */
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#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
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/* Power control/status register (PWR_CSR) */
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#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
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/* --- PWR_CR values ------------------------------------------------------- */
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/* Bits [31:9]: Reserved, must be kept at reset value. */
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/* DBP: Disable backup domain write protection */
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#define PWR_CR_DBP (1 << 8)
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/* PLS[7:5]: PVD level selection */
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#define PWR_CR_PLS_LSB 5
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/** @defgroup pwr_pls PVD level selection
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
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/**@}*/
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#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
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/* PVDE: Power voltage detector enable */
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#define PWR_CR_PVDE (1 << 4)
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/* CSBF: Clear standby flag */
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#define PWR_CR_CSBF (1 << 3)
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/* CWUF: Clear wakeup flag */
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#define PWR_CR_CWUF (1 << 2)
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/* PDDS: Power down deepsleep */
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#define PWR_CR_PDDS (1 << 1)
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/* LPDS: Low-power deepsleep */
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#define PWR_CR_LPDS (1 << 0)
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/* --- PWR_CSR values ------------------------------------------------------ */
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/* Bits [31:9]: Reserved, must be kept at reset value. */
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/* EWUP: Enable WKUP pin */
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#define PWR_CSR_EWUP (1 << 8)
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/* Bits [7:3]: Reserved, must be kept at reset value. */
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/* PVDO: PVD output */
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#define PWR_CSR_PVDO (1 << 2)
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/* SBF: Standby flag */
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#define PWR_CSR_SBF (1 << 1)
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/* WUF: Wakeup flag */
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#define PWR_CSR_WUF (1 << 0)
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/* --- PWR function prototypes ------------------------------------------- */
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BEGIN_DECLS
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void pwr_disable_backup_domain_write_protect(void);
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void pwr_enable_backup_domain_write_protect(void);
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void pwr_enable_power_voltage_detect(u32 pvd_level);
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void pwr_disable_power_voltage_detect(void);
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void pwr_clear_standby_flag(void);
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void pwr_clear_wakeup_flag(void);
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void pwr_set_standby_mode(void);
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void pwr_set_stop_mode(void);
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void pwr_voltage_regulator_on_in_stop(void);
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void pwr_voltage_regulator_low_power_in_stop(void);
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void pwr_enable_wakeup_pin(void);
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void pwr_disable_wakeup_pin(void);
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bool pwr_voltage_high(void);
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bool pwr_get_standby_flag(void);
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bool pwr_get_wakeup_flag(void);
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END_DECLS
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#if defined(STM32F1)
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# include <libopencm3/stm32/f1/pwr.h>
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#elif defined(STM32F2)
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# include <libopencm3/stm32/f2/pwr.h>
|
||||
#elif defined(STM32F4)
|
||||
# include <libopencm3/stm32/f4/pwr.h>
|
||||
#elif defined(STM32L1)
|
||||
# include <libopencm3/stm32/l1/pwr.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
|
||||
217
lib/stm32/common/pwr_common_all.c
Normal file
217
lib/stm32/common/pwr_common_all.c
Normal file
@ -0,0 +1,217 @@
|
||||
/** @defgroup STM32F1xx-pwr-file PWR
|
||||
|
||||
@ingroup STM32F1xx
|
||||
|
||||
@brief <b>libopencm3 STM32F1xx Power Control</b>
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 18 August 2012
|
||||
|
||||
This library supports the power control system for the
|
||||
STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**@{*/
|
||||
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Disable Backup Domain Write Protection.
|
||||
|
||||
This allows backup domain registers to be changed. These registers are write
|
||||
protected after a reset.
|
||||
*/
|
||||
|
||||
void pwr_disable_backup_domain_write_protect(void)
|
||||
{
|
||||
PWR_CR |= PWR_CR_DBP;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Re-enable Backup Domain Write Protection.
|
||||
|
||||
This protects backup domain registers from inadvertent change.
|
||||
*/
|
||||
|
||||
void pwr_enable_backup_domain_write_protect(void)
|
||||
{
|
||||
PWR_CR &= ~PWR_CR_DBP;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Enable Power Voltage Detector.
|
||||
|
||||
This provides voltage level threshold detection. The result of detection is
|
||||
provided in the power voltage detector output flag (see @ref pwr_voltage_high)
|
||||
or by setting the EXTI16 interrupt (see datasheet for configuration details).
|
||||
|
||||
@param[in] pvd_level u32. Taken from @ref pwr_pls.
|
||||
*/
|
||||
|
||||
void pwr_enable_power_voltage_detect(u32 pvd_level)
|
||||
{
|
||||
PWR_CR &= ~PWR_CR_PLS_MASK;
|
||||
PWR_CR |= (PWR_CR_PVDE | pvd_level);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Disable Power Voltage Detector.
|
||||
|
||||
*/
|
||||
|
||||
void pwr_disable_power_voltage_detect(void)
|
||||
{
|
||||
PWR_CR &= ~PWR_CR_PVDE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Clear the Standby Flag.
|
||||
|
||||
This is set when the processor returns from a standby mode.
|
||||
*/
|
||||
|
||||
void pwr_clear_standby_flag(void)
|
||||
{
|
||||
PWR_CR |= PWR_CR_CSBF;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Clear the Wakeup Flag.
|
||||
|
||||
This is set when the processor receives a wakeup signal.
|
||||
*/
|
||||
|
||||
void pwr_clear_wakeup_flag(void)
|
||||
{
|
||||
PWR_CR |= PWR_CR_CWUF;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Set Standby Mode in Deep Sleep.
|
||||
|
||||
*/
|
||||
|
||||
void pwr_set_standby_mode(void)
|
||||
{
|
||||
PWR_CR |= PWR_CR_PDDS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Set Stop Mode in Deep Sleep.
|
||||
|
||||
*/
|
||||
|
||||
void pwr_set_stop_mode(void)
|
||||
{
|
||||
PWR_CR &= ~PWR_CR_PDDS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Voltage Regulator On in Stop Mode.
|
||||
|
||||
*/
|
||||
|
||||
void pwr_voltage_regulator_on_in_stop(void)
|
||||
{
|
||||
PWR_CR &= ~PWR_CR_LPDS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Voltage Regulator Low Power in Stop Mode.
|
||||
|
||||
*/
|
||||
|
||||
void pwr_voltage_regulator_low_power_in_stop(void)
|
||||
{
|
||||
PWR_CR |= PWR_CR_LPDS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Enable Wakeup Pin.
|
||||
|
||||
The wakeup pin is used for waking the processor from standby mode.
|
||||
*/
|
||||
|
||||
void pwr_enable_wakeup_pin(void)
|
||||
{
|
||||
PWR_CSR |= PWR_CSR_EWUP;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Release Wakeup Pin.
|
||||
|
||||
The wakeup pin is used for general purpose I/O.
|
||||
*/
|
||||
|
||||
void pwr_disable_wakeup_pin(void)
|
||||
{
|
||||
PWR_CSR &= ~PWR_CSR_EWUP;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get Voltage Detector Output.
|
||||
|
||||
The voltage detector threshold must be set when the power voltage detector is
|
||||
enabled, see @ref pwr_enable_power_voltage_detect.
|
||||
|
||||
@returns boolean: TRUE if the power voltage is above the preset voltage
|
||||
threshold.
|
||||
*/
|
||||
|
||||
bool pwr_voltage_high(void)
|
||||
{
|
||||
return (PWR_CSR & PWR_CSR_PVDO);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get Standby Flag.
|
||||
|
||||
The standby flag is set when the processor returns from a standby state. It is
|
||||
cleared by software (see @ref pwr_clear_standby_flag).
|
||||
|
||||
@returns boolean: TRUE if the processor was in standby state.
|
||||
*/
|
||||
|
||||
bool pwr_get_standby_flag(void)
|
||||
{
|
||||
return (PWR_CSR & PWR_CSR_SBF);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get Wakeup Flag.
|
||||
|
||||
The wakeup flag is set when a wakeup event has been received. It is
|
||||
cleared by software (see @ref pwr_clear_wakeup_flag).
|
||||
|
||||
@returns boolean: TRUE if a wakeup event was received.
|
||||
*/
|
||||
|
||||
bool pwr_get_wakeup_flag(void)
|
||||
{
|
||||
return (PWR_CSR & PWR_CSR_WUF);
|
||||
}
|
||||
/**@}*/
|
||||
|
||||
@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
||||
ARFLAGS = rcs
|
||||
OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \
|
||||
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
|
||||
timer.o usb_f107.o desig.o pwr.o \
|
||||
timer.o usb_f107.o desig.o pwr_common_all.o \
|
||||
usb_fx07_common.o \
|
||||
gpio_common_all.o dma_common_f13.o spi_common_all.o \
|
||||
dac_common_all.o usart_common_all.o iwdg_common_all.o \
|
||||
|
||||
@ -32,6 +32,7 @@ ARFLAGS = rcs
|
||||
OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \
|
||||
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
|
||||
usb_f207.o adc.o dma.o \
|
||||
pwr_common_all.o \
|
||||
gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
|
||||
dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
|
||||
crc_common_all.o
|
||||
|
||||
@ -31,7 +31,7 @@ ARFLAGS = rcs
|
||||
OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o
|
||||
OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o
|
||||
OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o
|
||||
OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
|
||||
OBJS += pwr_common_all.o pwr.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/l1/pwr.h>
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
|
||||
void pwr_set_vos_scale(vos_scale_t scale)
|
||||
{
|
||||
@ -23,7 +23,7 @@
|
||||
|
||||
#include <libopencm3/stm32/l1/rcc.h>
|
||||
#include <libopencm3/stm32/l1/flash.h>
|
||||
#include <libopencm3/stm32/l1/pwr.h>
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
|
||||
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
|
||||
u32 rcc_ppre1_frequency = 2097000;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user