stm32: adc: group adc_registers

This commit is contained in:
Guillaume Revaillot 2019-11-08 14:47:11 +01:00 committed by Karl Palsson
parent 86b4cf6787
commit e7c8f18f7c
4 changed files with 12 additions and 0 deletions

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@ -35,6 +35,8 @@ specific memorymap.h header before including this header file.*/
#ifndef LIBOPENCM3_ADC_COMMON_V2_H #ifndef LIBOPENCM3_ADC_COMMON_V2_H
#define LIBOPENCM3_ADC_COMMON_V2_H #define LIBOPENCM3_ADC_COMMON_V2_H
/** @defgroup adc_registers ADC registers
@{*/
/* ----- ADC registers -----------------------------------------------------*/ /* ----- ADC registers -----------------------------------------------------*/
/** ADC interrupt and status register */ /** ADC interrupt and status register */
#define ADC_ISR(adc) MMIO32((adc) + 0x00) #define ADC_ISR(adc) MMIO32((adc) + 0x00)
@ -56,6 +58,7 @@ specific memorymap.h header before including this header file.*/
/** Common Configuration register */ /** Common Configuration register */
#define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8) #define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)
/**@}*/
/* --- Register values -------------------------------------------------------*/ /* --- Register values -------------------------------------------------------*/

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@ -42,6 +42,8 @@ specific memorymap.h header before including this header file.*/
* or only a much "simpler" version as found on (so far) f0 and l0. * or only a much "simpler" version as found on (so far) f0 and l0.
*/ */
/** @addtogroup adc_registers
*@{*/
/* ----- ADC registers -----------------------------------------------------*/ /* ----- ADC registers -----------------------------------------------------*/
/* Sample Time Register 2 */ /* Sample Time Register 2 */
#define ADC_SMPR2(adc) MMIO32((adc) + 0x18) #define ADC_SMPR2(adc) MMIO32((adc) + 0x18)
@ -84,6 +86,7 @@ specific memorymap.h header before including this header file.*/
/* ADC common (shared) registers */ /* ADC common (shared) registers */
#define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0) #define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0)
#define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xc) #define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xc)
/**@}*/
/* --- Register values ------------------------------------------------------*/ /* --- Register values ------------------------------------------------------*/
/* ADC_ISR Values -----------------------------------------------------------*/ /* ADC_ISR Values -----------------------------------------------------------*/

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@ -42,9 +42,12 @@ specific memorymap.h header before including this header file.*/
#ifndef LIBOPENCM3_ADC_COMMON_V2_SINGLE_H #ifndef LIBOPENCM3_ADC_COMMON_V2_SINGLE_H
#define LIBOPENCM3_ADC_COMMON_V2_SINGLE_H #define LIBOPENCM3_ADC_COMMON_V2_SINGLE_H
/** @addtogroup adc_registers
*@{*/
/* ----- ADC registers -----------------------------------------------------*/ /* ----- ADC registers -----------------------------------------------------*/
/** Channel Select Register */ /** Channel Select Register */
#define ADC_CHSELR(adc) MMIO32((adc) + 0x28) #define ADC_CHSELR(adc) MMIO32((adc) + 0x28)
/**@}*/
/* ----- ADC registers values -----------------------------------------------*/ /* ----- ADC registers values -----------------------------------------------*/
/* ADC_CFGR1 values */ /* ADC_CFGR1 values */

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@ -47,6 +47,8 @@
#define ADC_CHANNEL_VBAT 14 #define ADC_CHANNEL_VBAT 14
/**@}*/ /**@}*/
/** @addtogroup adc_registers
*@{*/
/* ----- ADC registers -----------------------------------------------------*/ /* ----- ADC registers -----------------------------------------------------*/
/** ADC_AWD1TR Watchdog 1 Threshold register */ /** ADC_AWD1TR Watchdog 1 Threshold register */
#define ADC_AWD1TR(adc) MMIO32((adc) + 0x20) #define ADC_AWD1TR(adc) MMIO32((adc) + 0x20)
@ -65,6 +67,7 @@
/** ADC_OR Option register */ /** ADC_OR Option register */
#define ADC_OR(adc) MMIO32((adc) + 0xD0) #define ADC_OR(adc) MMIO32((adc) + 0xD0)
/**@}*/
/* --- Register values -------------------------------------------------------*/ /* --- Register values -------------------------------------------------------*/