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BREAKING: stm32f0/f1: standardize flash_prefetch_xx

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use the same API on all families, flash_prefetch_{enable,disable}()
This commit is contained in:
Karl Palsson 2018-05-01 12:04:28 +00:00
parent 389ec82538
commit ef44bdd09e
3 changed files with 7 additions and 7 deletions
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4
include/libopencm3/stm32/common/flash_common_f01.h
View File

@ -98,8 +98,8 @@
BEGIN_DECLS BEGIN_DECLS
void flash_set_ws(uint32_t ws); void flash_set_ws(uint32_t ws);
void flash_prefetch_buffer_enable(void); void flash_prefetch_enable(void);
void flash_prefetch_buffer_disable(void); void flash_prefetch_disable(void);
void flash_unlock(void); void flash_unlock(void);
void flash_lock(void); void flash_lock(void);
void flash_clear_pgerr_flag(void); void flash_clear_pgerr_flag(void);

4
lib/stm32/common/flash_common_f01.c
View File

@ -37,7 +37,7 @@ the power-on low frequency mode before being set to a higher speed mode.
See the reference manual for details. See the reference manual for details.
*/ */
void flash_prefetch_buffer_enable(void) void flash_prefetch_enable(void)
{ {
FLASH_ACR |= FLASH_ACR_PRFTBE; FLASH_ACR |= FLASH_ACR_PRFTBE;
} }
@ -49,7 +49,7 @@ Note carefully the clock restrictions under which the prefetch buffer may be
set to disabled. See the reference manual for details. set to disabled. See the reference manual for details.
*/ */
void flash_prefetch_buffer_disable(void) void flash_prefetch_disable(void)
{ {
FLASH_ACR &= ~FLASH_ACR_PRFTBE; FLASH_ACR &= ~FLASH_ACR_PRFTBE;
} }

6
lib/stm32/f0/rcc.c
View File

@ -543,7 +543,7 @@ void rcc_clock_setup_in_hse_8mhz_out_48mhz(void)
rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_prefetch_buffer_enable(); flash_prefetch_enable();
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
/* PLL: 8MHz * 6 = 48MHz */ /* PLL: 8MHz * 6 = 48MHz */
@ -571,7 +571,7 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_prefetch_buffer_enable(); flash_prefetch_enable();
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
/* 8MHz * 12 / 2 = 48MHz */ /* 8MHz * 12 / 2 = 48MHz */
@ -597,7 +597,7 @@ void rcc_clock_setup_in_hsi48_out_48mhz(void)
rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_prefetch_buffer_enable(); flash_prefetch_enable();
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
rcc_set_sysclk_source(RCC_HSI48); rcc_set_sysclk_source(RCC_HSI48);