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Add a duty cycle count argument to i2c0_init() to adjust for changes in APB1 clock.

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Jared Boone 2012-10-17 11:47:03 -07:00 committed by Piotr Esden-Tempski
parent 18bcbc3d28
commit f4e45e74bc
2 changed files with 4 additions and 16 deletions
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2
include/libopencm3/lpc43xx/i2c.h
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@ -151,7 +151,7 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS BEGIN_DECLS
void i2c0_init(void); void i2c0_init(const uint16_t duty_cycle_count);
void i2c0_tx_start(void); void i2c0_tx_start(void);
void i2c0_tx_byte(uint8_t byte); void i2c0_tx_byte(uint8_t byte);
uint8_t i2c0_rx_byte(void); uint8_t i2c0_rx_byte(void);

18
lib/lpc43xx/i2c.c
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@ -41,25 +41,13 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc43xx/scu.h> #include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/cgu.h> #include <libopencm3/lpc43xx/cgu.h>
void i2c0_init(void) void i2c0_init(const uint16_t duty_cycle_count)
{ {
/* enable input on SCL and SDA pins */ /* enable input on SCL and SDA pins */
SCU_SFSI2C0 = SCU_I2C0_NOMINAL; SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
/* use IRC as clock source for APB1 (including I2C0) */ I2C0_SCLH = duty_cycle_count;
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); I2C0_SCLL = duty_cycle_count;
/* FIXME assuming we're on IRC at 12 MHz */
/* 400 kHz I2C */
I2C0_SCLH = 15;
I2C0_SCLL = 15;
/* 100 kHz I2C */
/*
I2C0_SCLH = 60;
I2C0_SCLL = 60;
*/
/* clear the control bits */ /* clear the control bits */
I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC