Add a duty cycle count argument to i2c0_init() to adjust for changes in APB1 clock.
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@ -151,7 +151,7 @@ LGPL License Terms @ref lgpl_license
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BEGIN_DECLS
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void i2c0_init(void);
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void i2c0_init(const uint16_t duty_cycle_count);
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void i2c0_tx_start(void);
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void i2c0_tx_byte(uint8_t byte);
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uint8_t i2c0_rx_byte(void);
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@ -41,25 +41,13 @@ LGPL License Terms @ref lgpl_license
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/cgu.h>
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void i2c0_init(void)
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void i2c0_init(const uint16_t duty_cycle_count)
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{
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/* enable input on SCL and SDA pins */
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SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
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/* use IRC as clock source for APB1 (including I2C0) */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
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/* FIXME assuming we're on IRC at 12 MHz */
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/* 400 kHz I2C */
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I2C0_SCLH = 15;
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I2C0_SCLL = 15;
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/* 100 kHz I2C */
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/*
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I2C0_SCLH = 60;
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I2C0_SCLL = 60;
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*/
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I2C0_SCLH = duty_cycle_count;
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I2C0_SCLL = duty_cycle_count;
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/* clear the control bits */
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I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC
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