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STM32F0: Fix PLL multiplication factor for 48MHz setup

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It was set to overclocking configuration!
This commit is contained in:
Onno Kortmann 2013-12-04 22:43:28 -08:00 committed by Karl Palsson
parent 868d65d872
commit f622437cfb
1 changed files with 2 additions and 2 deletions
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4
lib/stm32/f0/rcc.c
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@ -587,8 +587,8 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
/* 8MHz * 12 / 2 = 24MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16);
/* 8MHz * 12 / 2 = 48MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
RCC_CFGR &= RCC_CFGR_PLLSRC;