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Merge commit '7f947d724c552f896d5394f3ebbf6b47de9eb5a6' into sam-update

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This commit is contained in:
Jason Kotzin 2022-08-01 20:04:01 -07:00
commit fce7dd2957
4 changed files with 23 additions and 18 deletions
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25
src/platforms/stlink/platform.c
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@ -68,9 +68,8 @@ void platform_init(void)
GPIO_CNF_OUTPUT_PUSHPULL, TCK_PIN); GPIO_CNF_OUTPUT_PUSHPULL, TCK_PIN);
gpio_set_mode(TDI_PORT, GPIO_MODE_OUTPUT_50_MHZ, gpio_set_mode(TDI_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, TDI_PIN); GPIO_CNF_OUTPUT_PUSHPULL, TDI_PIN);
gpio_set(SRST_PORT, srst_pin);
gpio_set_mode(SRST_PORT, GPIO_MODE_OUTPUT_50_MHZ, platform_srst_set_val(false);
GPIO_CNF_OUTPUT_OPENDRAIN, srst_pin);
gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_2_MHZ, gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_2_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, led_idle_run); GPIO_CNF_OUTPUT_PUSHPULL, led_idle_run);
@ -90,21 +89,17 @@ void platform_init(void)
void platform_srst_set_val(bool assert) void platform_srst_set_val(bool assert)
{ {
uint32_t crl = GPIOB_CRL;
uint32_t shift = (srst_pin == GPIO0) ? 0 : 4;
uint32_t mask = 0xf << shift;
crl &= ~mask;
if (assert) { if (assert) {
/* Set SRST as Open-Drain, 50 Mhz, low.*/ gpio_set_mode(SRST_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIOB_BRR = srst_pin; GPIO_CNF_OUTPUT_OPENDRAIN, srst_pin);
GPIOB_CRL = crl | (7 << shift); gpio_clear(SRST_PORT, srst_pin);
while (gpio_get(SRST_PORT, srst_pin)) {};
} else { } else {
/* Set SRST as input, pull-up. gpio_set_mode(SRST_PORT, GPIO_MODE_INPUT,
* SRST might be unconnected, e.g on Nucleo-P!*/ GPIO_CNF_INPUT_PULL_UPDOWN, srst_pin);
GPIOB_CRL = crl | (8 << shift); gpio_set(SRST_PORT, srst_pin);
GPIOB_BSRR = srst_pin; while (!gpio_get(SRST_PORT, srst_pin)) {};
} }
while (gpio_get(SRST_PORT, srst_pin) == assert) {};
} }
bool platform_srst_get_val() bool platform_srst_get_val()

11
src/target/adiv5_swdp.c
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@ -170,6 +170,17 @@ static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
raise_exception(EXCEPTION_ERROR, "SWDP Parity error"); raise_exception(EXCEPTION_ERROR, "SWDP Parity error");
} else { } else {
swdptap_seq_out_parity(value, 32); swdptap_seq_out_parity(value, 32);
/* RM0377 Rev. 8 Chapter 27.5.4 for STM32L0x1 states:
* Because of the asynchronous clock domains SWCLK and HCLK,
* two extra SWCLK cycles are needed after a write transaction
* (after the parity bit) to make the write effective
* internally. These cycles should be applied while driving
* the line low (IDLE state)
* This is particularly important when writing the CTRL/STAT
* for a power-up request. If the next transaction (requiring
* a power-up) occurs immediately, it will fail.
*/
swdptap_seq_out(0, 2);
} }
return response; return response;

2
src/target/cortexm.c
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@ -414,8 +414,6 @@ void cortexm_detach(target *t)
/* Disable debug */ /* Disable debug */
target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
/* Add some clock cycles to get the CPU running again.*/
target_mem_read32(t, 0);
} }
enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR }; enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };

3
src/target/nrf51.c
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@ -166,7 +166,8 @@ bool nrf51_probe(target *t)
case 0x00AC: /* nRF52832 Preview QFAA BA0 */ case 0x00AC: /* nRF52832 Preview QFAA BA0 */
case 0x00C7: /* nRF52832 (rev 1) QFAA B00 */ case 0x00C7: /* nRF52832 (rev 1) QFAA B00 */
case 0x00E3: /* nRF52832 (rev 1) CIAA B?? */ case 0x00E3: /* nRF52832 (rev 1) CIAA B?? */
case 0x0139: /* nRF82832 (rev 2) ??AA B?0 */ case 0x0139: /* nRF52832 (rev 2) ??AA B?0 */
case 0x014F: /* nRF52832 (rev 2) CIAA E1 */
t->driver = "Nordic nRF52"; t->driver = "Nordic nRF52";
target_add_ram(t, 0x20000000, 64*1024); target_add_ram(t, 0x20000000, 64*1024);
nrf51_add_flash(t, 0x00000000, 512*1024, NRF52_PAGE_SIZE); nrf51_add_flash(t, 0x00000000, 512*1024, NRF52_PAGE_SIZE);