Now that the big pieces of the adc-v2 common files are in place, start
including l0 in the builds. This includes only the very very basic core v2
peripheral functions, and the very basic definitions.
The adc v2 periph has the same register map, but comes in two flavours, one
supporting injected channels, more watchdogs, per channel sampling times and
so on, and one "simple" version.
Pull up the f3 and f0 portions into the appropriate files, after comparing with
L0 and L4 reference manuals, even if those are not fully landed yet.
The f0, f30x and l0 have a very similar "v2" adc peripheral.
Start extracting out some of the common code, and fix the glaring bug in
adc_power_down that was affecting them both.
This is not intended to be a fully comprehensive extraction, just the first
easy steps.
The adc peripheral on F30x is the same as F0, L0 and L4. In the reference
manuals, the following names are used.
F3: CFGR (no CFGR2)
F0 and L0: CFGR1 and CFGR2
L4: CFGR and CFGR2
Moving to a single consistent name, that's more likely to be inline with future
part numbers makes it much easier to extract common driver code for the
peripheral.
While all bit defines are moved to the CFGR1 style, core register definitions:
ADC_CFGR(adc) and ADCx_CFGR are kept to match the original register name in the
reference manual.
Fixes Github issue #548
There are as many SMPRx registers are needed for channels supported, and on all
other families, the field definitions are just ADC_SMPR_SMP_XXX. For
consistency, and to avoid any confusion or duplication, use the same style here
too. Drop silly unused per channel definitions that have no purpose.
At least temp sensor, vrefint and vbat/vlcd should have consistent names and
consistent doxygen.
Dropped channel definitions that are the same as the raw number.
It's not used anywhere, and if this sort of api becomes needed, it can be
designed cleanly and finished.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
All defined bits are rc_w0.
The paranoid version of this would write 0 to the reserved bits (0 is the
"reset value"), but this would require knowing which flags are valid on the
actual platform, and adding the corresponding macros.
This is more in line with the actual hardware (u32 registers), and will still
work if PRIMASK or FAULTMASK ever have more than 1 bit defined.
The functions cm_is_masked_interrupts() and cm_is_masked_faults() are
unchanged, since returning 'bool' fits with the function naming.
Fixes most of github issue #475. What remains "unfixed" is the absence
of functions to simply 'get' the u32 value of PRIMASK and FAULTMASK registers.
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly
and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM)
Remove the duplicate here.
The MPU RASR Shareable, Bufferable and Cacheable bits are all individual
bits, and none of the existing defines appear to even match the ARM
documentation. Remove them, but leave the definitions of the bit
positions.
Reported by MightyPork on IRC
Connectivity line devices have more remaps available, and the existing code was
artificially and needlessly preventing those remaps from being set, even if
defined.
While implementing this, the existing code to handle SWJ remap was found to be
inconsistent with the reference manual and has been fixed.
Fixes github issue #369
Instead of having committed files containing a single developer's serials, use
optional includes to include a local config file for each board.
If you have only a single board connected, simply:
$ make -f Makefile.<board> clean all flash
If you have multiple boards connected, make sure to fill in the appropriate
hla_serial in your openocd.<board>.local.cfg file, and then run the same
commands.
Original commits, while appearing clean and tidy, hadn't even been
compile tested. Trust no-one. Not even Scully.
Fixes: 770878e7b4ac12513e121e087261ca0972ba04e6
Fixes: 86d20ef00c00a14d7a4f0b834b9b608b2dd3638a
Fixes: 05ff0df32226dc28e22b98afde07bb886af9ddc9
DESIG_FLASH_SIZE is provided for all stm32 parts in desig.h, correctly defined
as 16bits. Remove the incorrect duplicate definition within the f1 flash
handling code.
Fixes github issues #621
Recent debian testing and ubuntu 15.10 releases contain a
gcc-arm-none-eabi toolchain that returns 0 for the test with -mcpu and
-fsyntax-only, despite not actually supporting cortex-m7. They then
failed hard on actual compilation steps.
Use the --help=target output instead. tested with old g-a-e 4.7 and
newer releases.
f7 has -mfpu=fpv5-sp-d16 in the lib makefile, devices.data should have
the same setting.
l0 is a cortex m0+, not a cortex m0, and uses cortex-m0plus in the
library makefile, and should have the same setting in the devices.data
file.
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation:
-multiple calls to cm_is_masked_interrupts() in the same scope/context
- -Os or -O2 optimization
This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts().
Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
Fails when the mutex was already locked.
Implemented zyp's fix for broken mutex. If it's 1 (= failure) by default, the function works fine.
irc log for reference
```
<zyp> strex returns 1 if it fails, 0 if it's successful
<zyp> but if the mutex is already locked, line 57 skips the status update and status gets remains at the initial value which means successful, which is wrong
<zyp> changing line 54 to status = 1 should do the trick
```
The F429i board has the user USB OTG port connected to the HS capable
OTG core, rather than the FS OTG core. It is still only operating in FS
mode, as you need a ULPI phy to use HS mode.
