This _breaks_ your gpio code for F2 and F4. It makes them consistent
with the reference manual, and more consistent with all other families
and general expectations.
OLD code -> NEW code
RCC_AHB1RSTR_IOPxRST -> RCC_AHB1RSTR_GPIOxRST
RCC_AHB1ENR_IOPIxEN -> RCC_AHB1ENR_GPIOxEN
RCC_AHB1LPENR_IOPxLPEN -> RCC_AHB1LPENR_GPIOxLPEN
[We're not actually breaking it, see the next commit for deprecated
aliases]
Makefile doesn't even refer to it, and it's empty anyway. Not required
for doxygen purposes, (anymore?) so just drop it. File had _never_ been
included in the f3 makefile.
The ADC v2 peripheral doesn't have the same behaviour of starting, where
the hardware clears the bit immediately, on v2, it is not cleared until
the ADC is stopped, or the end of sequence flag is set.
Fixes https://github.com/libopencm3/libopencm3/issues/557
The SPI br parameter has always been the 3 bit fpclk divider field, and
was never a target or explicit bit rate. Correct the comments, and drop
the duplicate commentary that wasn't included in the doxygen output
anyway.
Fixes: a7a3770d Add initial SPI code
Until https://github.com/libopencm3/libopencm3/issues/732 has been
fixed, it's not enough to just have it in the README that you need GNU
awk. Explicitly use the "gawk" command name. This exists on (sane)
systems that have gawk as awk, and for systems that use mawk as default,
the gawk name should also exist.
This should make it significantly easier to diagnost the cause of build
problems.
Final chunk of register definitions to be pulled up.
Now the "target" files are _only_ defining the list of u(s)arts
available, and any _specific_ functions for that target.
Just small pieces at a time to make it easy to see what's happening.
Taking definitions currently implemented in both f0/f3 headers and
making combined, documented versions in the -v2 header.
Use the usart-common base plus the usart-v2 code, instead of private
implementations. Less code, more common apis across targets.
Of note is the trick to make F0 look like it has an APB2 bus. It's the
only stm32 that doesn't have a documented APB2 bus, but still has
peripherals enabled via an "APB2" register, and they match how other
targets have an APB2. Simply make APB2 an alias of APB1, as it's only
used for clock speed detection.
Instead of declaring that _every_ device has USART1,2,3 and UART4,5, let
the targets themselves define what periphs they do, along with their
USARTx_BASE defines, and let the common headers just have the common
abstractions.
