Use EP0 OUT flow control to NAK OUT packets when we're not yet expecting
any. This prevents the status OUT event from arriving while the control
state machine is still expecting the data IN completion event.
Attempt to be more brutal by delaying more often, instead of always
promptly servicing the usb stack.
This is implemented via using timer6 to do a known number of
microseconds busy delay, and so only works on platforms that have
reached at least core timer functionality, and provide the
rcc_apb1_frequency variable.
NOTE! This will _fail_ on devices using the st_usbfs drivers at present,
but the code _should_ work, and the tests land to verify that the
library fix, fixes the problem. (see subsequent commit)
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
Originally suggested in https://github.com/libopencm3/libopencm3/pull/399
At least provide macros for each family that allows easy masking of the
full set of reset reason flags. Trying to provide a function that
provides these in random upper bits seems unclear at best.
Reserved bits are marked explicitly in the comments. ASCR defines
are changed to be consistent with the reference manual. HYSCR,
ASMR, CMR and CICR register defines are rewritten to be more
concise and readable.
For both v1 and v2, provide routines to help do arbitrary length
write/read transfers.
Tested with multiple byte writes and reads, for both 100khz and 400khz,
with repeated starts and stop/starts. However, only tested (presently)
with a single i2c target device, a Sensiron SHT21 sensor. Extended
testing against eeproms and alternative devices would be useful
Use REBASE(OTG_FIFO(endpoint)) to access the FIFO.
For the receive FIFO do not use the endpoint. There
is only one receive FIFO so giving the endpoint is
a no-op.
Get rid of REBASE_FIFO macro.
When reading a portion of the packet that is not divisible by 4 and
not equal to rxbcnt the count could get off, since 4 bytes are read
from the fifo in the last step but rxbcnt was only updated by the
number of bytes the caller requested.
We fix this by always subtracting four bytes (the number of bytes
read from the fifo) when we read a word from the fifo. Care has
to be taken in the last step so that rxbcnt doesn't underflow (it
is an unsigned number).
Note that reading in several small chunks not divisible by 4 doesn't
work as the extra bytes read in the last step are always discarded.
After a SETUP packet on a control endpoint the transmit FIFO
should usually be empty. If something bad happened, e.g. PC
and device got out of sync, we want to clear the fifo.
This should fix#668.
This is to interrupt for setup sequences on IN packet before
checking for OUT packet received. This fixes the problem that
usb_control_out stalls because we are not yet in STATUS_OUT phase.
Related to #668.
If you're interested in slightly underclocking or midrange speeds,
you're into custom environments. Drop all the "helpers" for these odd
speeds. This is not the max speed for any existing f0 part.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
The following four new functions enable clocking SoC from HSE crystal:
rcc_clock_setup_in_hse_8mhz_out_{8,16,32,48}mhz
These functions start HSE as external clock and feed its output to PLL
if higher frequency is needed.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
-> Dropped 8,16,32Mhz functions as superfluous.
- add brief descriptions for HSI clock functions
- use rcc_set_pll_source to set PLL source in RCC_CFGR
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
