All defined bits are rc_w0.
The paranoid version of this would write 0 to the reserved bits (0 is the
"reset value"), but this would require knowing which flags are valid on the
actual platform, and adding the corresponding macros.
This is more in line with the actual hardware (u32 registers), and will still
work if PRIMASK or FAULTMASK ever have more than 1 bit defined.
The functions cm_is_masked_interrupts() and cm_is_masked_faults() are
unchanged, since returning 'bool' fits with the function naming.
Fixes most of github issue #475. What remains "unfixed" is the absence
of functions to simply 'get' the u32 value of PRIMASK and FAULTMASK registers.
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly
and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM)
Remove the duplicate here.
The MPU RASR Shareable, Bufferable and Cacheable bits are all individual
bits, and none of the existing defines appear to even match the ARM
documentation. Remove them, but leave the definitions of the bit
positions.
Reported by MightyPork on IRC
Connectivity line devices have more remaps available, and the existing code was
artificially and needlessly preventing those remaps from being set, even if
defined.
While implementing this, the existing code to handle SWJ remap was found to be
inconsistent with the reference manual and has been fixed.
Fixes github issue #369
Instead of having committed files containing a single developer's serials, use
optional includes to include a local config file for each board.
If you have only a single board connected, simply:
$ make -f Makefile.<board> clean all flash
If you have multiple boards connected, make sure to fill in the appropriate
hla_serial in your openocd.<board>.local.cfg file, and then run the same
commands.
Original commits, while appearing clean and tidy, hadn't even been
compile tested. Trust no-one. Not even Scully.
Fixes: 770878e7b4ac12513e121e087261ca0972ba04e6
Fixes: 86d20ef00c00a14d7a4f0b834b9b608b2dd3638a
Fixes: 05ff0df32226dc28e22b98afde07bb886af9ddc9
DESIG_FLASH_SIZE is provided for all stm32 parts in desig.h, correctly defined
as 16bits. Remove the incorrect duplicate definition within the f1 flash
handling code.
Fixes github issues #621
Recent debian testing and ubuntu 15.10 releases contain a
gcc-arm-none-eabi toolchain that returns 0 for the test with -mcpu and
-fsyntax-only, despite not actually supporting cortex-m7. They then
failed hard on actual compilation steps.
Use the --help=target output instead. tested with old g-a-e 4.7 and
newer releases.
f7 has -mfpu=fpv5-sp-d16 in the lib makefile, devices.data should have
the same setting.
l0 is a cortex m0+, not a cortex m0, and uses cortex-m0plus in the
library makefile, and should have the same setting in the devices.data
file.
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation:
-multiple calls to cm_is_masked_interrupts() in the same scope/context
- -Os or -O2 optimization
This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts().
Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
Fails when the mutex was already locked.
Implemented zyp's fix for broken mutex. If it's 1 (= failure) by default, the function works fine.
irc log for reference
```
<zyp> strex returns 1 if it fails, 0 if it's successful
<zyp> but if the mutex is already locked, line 57 skips the status update and status gets remains at the initial value which means successful, which is wrong
<zyp> changing line 54 to status = 1 should do the trick
```
The F429i board has the user USB OTG port connected to the HS capable
OTG core, rather than the FS OTG core. It is still only operating in FS
mode, as you need a ULPI phy to use HS mode.
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
This has hurt many many many people over it's lifetime, by confusing their
multilib toolchains. Simply drop it outright. People who _really_ know what
they're doing are still perfectly entitled to "install" portions of this
project in suitable locations for their own use.
These prototypes affect functions defined by application code. Only
the implementations in libopencm3 are supposed to be weak; the
functions in application code should definitely not be. Otherwise,
you'll end up with two weak symbols being linked together, and
it's luck as to which one the linker picks.
Just the basic core common functionality gained for free by being a common
peripheral. Enough for a miniblink.
Fixes some errors in the GPIO memory map. ST's naming of AHB2 vs AHB3 is
confusing.
Don't include any of the common files yet, we're only getting a stub framework
up for further work.
This is mostly noise adding links from the other families to make the l4
"exist"
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.
Only stub support so far, but this opens up the beginning of build testing.
Many stm32 families have multiple ADC and DAC peripherals. F0 (so far) only
has one. To make it easier to use the same code on many stm32 families,
provide an alias for ADC1 to ADC.
After adding support to the f3, add missing doxygen support to the f0
equivalent. This improves things and keeps them consistent until/if they are
pulled out as common code.
Based on the f0 support, which has identical functionality, but with doxygen
added. Bits renamed as they are only HSE prediv on some targets, and makes
things more consistent with the f0.
Fixes part of github issue #560
