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428 Commits

Author SHA1 Message Date
Uwe Bonnes
acec489647 adiv5_jtagdp: Always set idcode. 2020-11-29 21:11:11 +01:00
Uwe Bonnes
f45c56af83 adiv5/swdp: Check early for valid DP idcode. 2020-11-29 15:48:50 +01:00
Uwe Bonnes
7df314e265 Firmware/Jlink: Fix double free when debug power-up fails (#780) 2020-11-29 15:48:50 +01:00
Uwe Bonnes
bf548e92c0 swd: After write low_access, always append 8 clk to move data through SW-DP. 
Especially needed when leaving the debugger or during debug unit power-up.

ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
tells to clock the data through SW-DP to either :
- immediate start a new transaction
- continue to drive idle cycles
- or clock at least 8 idle cycles

Implement last option to favour correctness over slight speed decrease

Implement only for adapters where we assemble the seq_out_parity in our code,
as on firmware, ftdi and jlink. Hopefully the high level adapters do it right.

Reverts 2c33cde63fe779d3019fe8f63dd4420cb960bbfe and
cde7726b8730242cd40a9974d129b46af80c68af
 2020-11-27 22:26:48 +01:00
Uwe Bonnes
3ee31473c6 cortexm.c: LPC15xx has designer 43b and Partno 4c3 
Thanks to JojoS!
 2020-11-27 22:26:48 +01:00
Uwe Bonnes
19e1fddba2 adiv5: Remove unnescessary read. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
cda83d3084 Fix memleaks. 
Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
 2020-11-27 22:26:48 +01:00
Uwe Bonnes
9ac5adfcef adiv5: Additional decoding. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
d78d7838d3 stm32f1: Always read DBGMCU_IDCODE for t->idcode (#770) 
At least STM32F042 has 0x440 as romtable partno vs 0x445 as DBGMCU_IDCODE.
Thanks to Andrey Melnikov(aam335) for pointing out!
 2020-11-27 22:26:48 +01:00
Uwe Bonnes
653d486ee2 cortexm: Store CPUID in target structure. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
80154c5c7a adiv5_swdp: Fix more memory leak. 2020-11-27 22:26:48 +01:00
Noah Pendleton
35bcb4f7c6 Switch on the lpc546xx target 
Enable the lpc546xx target. Tested on the LPCXpresso54628 dev board,
able to flash and debug.
 2020-11-24 21:32:39 +01:00
Sean Cross
e9c02296f2 target: kinetis: add S32K118 
This adds support for the NXP S32K118. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-11-14 13:06:23 +01:00
jbuonagurio
f18be6ef7a Add support for Kinetis K12 and placeholders for other K-series MCUs 2020-11-07 12:44:05 +01:00
Uwe Bonnes
2c33cde63f cortexm.c/cortexm_halt_resume: Add some clock cycles to always get CPU going (#768) 2020-11-01 21:53:23 +01:00
Uwe Bonnes
1f7a716710 adiv5.c: Run cortexm_prepare on all suspected CortexM instances. 
Gets all debug units of the second CPU of a STM32H745 visible.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes
18673d9a56 adiv5: Rework DP/AP refcounting. 
ASAN non longer reports leaks with the STM32H745.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes
f76a7c4e92 adiv5: Release devices after scan. 
Before, scanning only kept device stopped until POR or attach/detach cycle.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes
59dc1b7eb4 cortex-m7: Give hint about buggy core revision. 2020-10-23 09:40:15 +02:00
Uwe Bonnes
976c763747 jtag remote: Start fixing handling M0 (second jtag) for LPC4322 in high-level 
- LPC11: Only print none-null unknown idcodes.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes
c161521c26 cortexm: Designer ARM must be in the default path when probing. 2020-10-23 09:40:15 +02:00
Uwe Bonnes
cdd07544d5 Cortexm: Allow pure debug on devices not yet handled for flashing 
- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
 2020-10-23 09:40:15 +02:00
Uwe Bonnes
0ffb4f7b18 cortexm: Fix protected SAM detection 
- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
 2020-10-17 12:49:37 +02:00
Uwe Bonnes
5bc743d221 samd: Propagate security after setting security by chip reset. 2020-10-17 12:49:37 +02:00
Uwe Bonnes
8b929c12c9 hosted/jtag: Transfer jtag_devs to firmware. 2020-10-16 20:03:03 +02:00
Uwe Bonnes
3d92b82678 jtag: Use index and not device structure for jtag_dev_write_ir and jtag_dev_shift_dr 2020-10-16 20:03:03 +02:00
Uwe Bonnes
7ccf0d3e03 jtag_dev_t: Make dev, idcode and desc less generic. 
No codechange intended.
 2020-10-16 20:03:03 +02:00
Uwe Bonnes
87b546777a nrf51: Be more verbose about the protection status. 2020-10-16 12:16:33 +02:00
Richard Meadows
4108b649c2 stm32h7: Add support for new product lines 
Add support for:
* STM32H7B3/B0/A3 (RM0455)
* STM32H723/33/25/35/30 (RM0468)

Successfully tested with:
* STM32H7A3ZIT (RM0455)
* STM32H747XIH (check for regressions)
 2020-10-10 22:09:34 +02:00
Uwe Bonnes
877b4be8ee cortexm: Restrict probing by using the ap_designer. 
More designers need to be observed and reported by users and added.
Request users to send needed data.
 2020-10-07 20:12:35 +02:00
Uwe Bonnes
91d1ef8bf6 target/stm32: Use t->idcode with probe. 2020-10-07 20:12:35 +02:00
Uwe Bonnes
44bfb62715 Adiv5: Print Designer/Partno when device is not recognized 
t->idcode is now 16 bit.
 2020-10-07 20:12:35 +02:00
Uwe Bonnes
c456fc7f61 adiv5: Store AP designer and partno in the AP structure. 2020-10-07 20:12:32 +02:00
Uwe Bonnes
159196c2ad Cortexm: Remove forced_halt. 2020-10-07 20:11:33 +02:00
Uwe Bonnes
9bb2807706 adiv5/romtable: Prepare CortexM devices to read the ROMTABLE 
It seems, writing to DHCSR fails silent when the device is sleeping.
Reading DHCS during sleep may return nonsense.
Repeated write may at some point catch the device running and succeed.
With devices sleeping for long time and running on faster clock the
chance for a successful hotplug gets smaller.

- Try hard to halt a sleeping device
- Prepare vector catch and enable all debug units by TRACENA
- Release reset
- Apply device specific fixes
-- STM32F7: Store old value of DBGMCU_CR, enable debug in sleep in
   DBGMCU before reading PIDR and restore DBGMCU on detach.

Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
 2020-10-07 20:11:17 +02:00
Gareth McMullin
dc8924a2bc
stm32h7: Don't tc_printf from flash functions (#747) 
* stm32h7: Don't tc_printf from flash functions

Receving an 'O' packet while flashing confuses GDB and then
weird stuff happens.

* Replace tc_printf with DEBUG_WARN
 2020-10-05 10:45:18 +02:00
Uwe Bonnes
014abf6cc9 adiv5.c: Reduce number of errors if reading cidr fails. 2020-10-01 15:33:28 +02:00
Uwe Bonnes
be40d2b851 adiv5: Check Debug Base Address early 
Reduces printout when scanning the romtable
 2020-10-01 15:22:17 +02:00
Eivind Alexander Bergem
38bc5bbf82 Add LPC546xx support #741 #553 2020-09-30 12:56:53 +02:00
Uwe Bonnes
2fdd94adeb STM32F7: Add another missing Arch ID. 2020-09-24 16:20:34 +02:00
Uwe Bonnes
bdb351a6ea adiv5_swdp: On ACK_FAULT, error() and try again once #731 
when writing CSW.
 2020-09-18 20:07:32 +02:00
Damien Merenne
120b3134bb Add SAM4SD32C/B support. 2020-09-07 17:36:15 +02:00
Uwe Bonnes
8a2bce26f2 Hosted: Fix memory leak when platform_swdptap_init fails. 2020-09-04 11:49:13 +02:00
David Lawrence
f65afb1588 Use correct IAP entry address for LPC84x 2020-08-14 20:00:18 +02:00
Uwe Bonnes
71e9d78210 adiv5.c: Add another ARCH_ID found STM32F205. 2020-08-01 14:00:17 +02:00
Uwe Bonnes
1b12e407fd adiv5: Add missing arch identifiers for Cortex-M7 ETM. 2020-07-31 11:53:15 +02:00
Francesco Valla
696daa8352 adiv5: fix debug print of dev_type 
Since dev_type is an 8 bit unsigned integer, use the PRIx8 macro instead
of PRIx32.
 2020-07-29 11:32:24 +02:00
Uwe Bonnes
726d4b4496 adiv5.c: Add missing DEVTYPE and ARCHID to some existing PIDRs(#698,#699) 
Probably more additions are needed.
 2020-07-14 16:26:32 +02:00
Uwe Bonnes
09ceaea70f adiv5_swdp: Fix another memory leak. 2020-07-14 15:02:13 +02:00
Fredrik Ahlberg
7ebb94d134 cortexm: Add comment on CPUID register 2020-07-12 22:54:39 +02:00