rcc_set_pll_divisor() would take the number we wanted to divide the 400MHz
clock and put it directly in the RCC2 register. This caused the clock to always
be one speed tier slower than expected. The value of the divisor must be
decremented by 1, so a divisor of 5 will be written as 4 in the RCC2.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
to remove errors, duplications and inconsistencies.
File lib/stm32/f1/pwr.c - all code removed as it duplicates that in common/pwr_common.c
Remaining changes do not affect code. Compiles OK.
TODO efm32 has no code so generates no modules
TODO F2 needs pwr.c
TODO L1 needs dma.h and dma.c
Add an abstraction layer to handle the clock control for the run time clock on
LM4F (RCC). Sleep and deep-sleep clock configuration is not handled.
Complete documentation for the clock control API is included in doxygen-style
comments, and is included in [doc].
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Conflicts:
lib/lm4f/Makefile
