Add the register definitions and some of the most basic helper functions
for the new style BCD RTC module found on the F2, F4, L1, F3 and F0.
This tries to keep as close to HACKING_COMMON_DOC as possible, while
maintaining sane names.
Code added for L1 to support the PWR Control block didn't properly
follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and
some headers were missing. This commit has no functional changes, it
only addresses the style and structure problems.
Earlier additions to the L1 support were not correctly using linux
coding guidelines as specified in /HACKING.
Some examples were also missing license information.
Fixes#51
There should be no reason for manually trying to load the stack. Cortex
devices can be programmed with only C, and any code that needed this
would indicate broken vectors.
the "make clean" target showed a constant "stm32/f1" debug message
instead of the current relative directory. this is fixed by showing the
relevant portion of the current directory instead, relevant being
determined by evaluating the current makefile's relative position and
stripping that part off.
Flashes the Red, Green and Blue diodes on the board, in order. The system clock
starts at 80MHz.
Pressing SW2 toggles the system clock between 80MHz, 57MHz, 40MHz ,20MHz, and
16MHz by changing the PLL divisor.
Pressing SW1 bypasses the PLL completely, and runs off the raw 16MHz clock
provided by the external crystal oscillator.
The LEDs will toggle at different speeds, depending on the system clock. The
system clock changes are handled within the interrupt service routine.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Instead of setting and clearing RGB pins by PINx constants, define more readable
constants such as RGB_RED, and RGB_PORT.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add an abstraction layer to handle the clock control for the run time clock on
LM4F (RCC). Sleep and deep-sleep clock configuration is not handled.
Complete documentation for the clock control API is included in doxygen-style
comments, and is included in [doc].
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Conflicts:
lib/lm4f/Makefile
The enum definitions are specified in the form
31:5 register offset from SYSCTL_BASE for the clock register
4:0 bit offset for the given peripheral
The names have the form [clock_type]_[periph_type]_[periph_number]
Where clock_type is
RCC for run clock
SCC for sleep clock
DCC for deep-sleep clock
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Updated the documentation so that it appears in all families
Also added it to the L1 area, but is untested. An addition to the memorymap
allows commonality and a #ifdef added to the spi_common_all code to
exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those.
An rcc dispatch header was added to remove same code from the spi header.
In the header:
- Fix DMA_SxCR_CT: change shift from 18 to 19
For use with the convenience functions:
- Added DMA_SxCR_CHSEL generic values
- Added DMA_STREAM - generic values
- Added dma_if_offset - rather than separating out LISR and HISR
- Added masks
- Added dma_disable_double_buffer_mode()
There was no reference to LM4F in in the doc/ subdirectory. Add the needed
infrastructure to generate focumentation for LM4F.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The LM4F provides new registers for system control. Each peripheral
now has its own clock gating control register. The LM4F still supports
the legacy registers for backwards compatibility.
Use SYSCTL_RCGCGPIO instead of SYSCTL_RCGC to enable the GPIO.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add an "#ifdef(LM4F)" clause to include/libopencm3/dispatch/nvic.h
and lib/dispatch/vector_nvic.c. This compiles in the vector table
and allows interrupts to be used.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Specify the -mfloat-abi=hard and -mfpu=fpv4-sp-d16 flags so that FPU
is enabled by default.
While this compiles with FPU support, in order to use the floating point types,
the FPU must be explicitly enabled at runtime.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Fix three distinct issues were present with
examples/lm4f/Makefile.include:
1. Architecture flags were not being passed to the linker. This caused the linker
to link against the wrong libraries when trying to use any C library, causing
hard faults.
2. -lc and -lnosys were not linked against. Try using printf() without -lnosys
3. The makefile erroneously specified -mcpu=cortex-m3 instead of m4.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Create lm4f code infrastructure from the lm3s infrastructure.
As far as the interrupt table is concerned, don't create an irq.yaml. Just
include the LM3S nvic.h. The LM3S vector table seems to be compatible with the
LM4F
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This has only been tested functionally with basic timers, and basic operations.
Advanced timer support has been #ifdefed to compile, but this probably needs more testing.
Despite the L1 being a low power device, my initial focus is on making
it basically compatible with existing devices.
To that end, provide clock setup helper routines that configure it for maximum performance,
allowing some similar clock speeds to F1 devices to help with testing. This requires adding
the power chipset routines to set the voltage range.
Clock setup style is similar to the F4 code, which seems nicer than the overflow of different
routines used on the F1 code.
NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power
code, even though it should be compatible
