74 Commits

Author SHA1 Message Date
larchuto
0a68b012a1 stm32l4: Fix typo impacting uart4 and uart5 2019-11-21 18:59:32 +01:00
Guillaume Revaillot
811aebf096 stm32: lptimer: enable lptimer.h usage on f4,f7,l4 and g0 chips. 2019-07-05 10:48:55 +02:00
Guillaume Revaillot
e06898d9a4 stm32: dma: cselr: factorize register definition.
F09x and L4 share the same cselr register, as well as some L0s, factorize
definitions in a new shared header and add helpers.

fyi, that register allows to redefine dma channel peripheral mapping - see
device datasheet for mapping tables.
2019-06-17 11:44:44 +00:00
Eric Van Albert
3d422a930f stm32l4: add common DAC support
Replace the DAC1_BASE style, only used on l4 with the standard DAC_BASE
used on all other targets.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2019-06-12 23:25:22 +00:00
Karl Palsson
867bd164eb doc:stm32: usart: fix grouping and heirarchy of base addrs
They were always landing on the top level, or not even present.
2019-06-12 23:06:22 +00:00
Karl Palsson
5ba8d94b81 doc: stm32l4: rcc: add groupings for periph resets
As we did with f2, use a parent grouping to contain the different sets
of APB1 fields.
2019-06-12 22:56:38 +00:00
Karl Palsson
ce5d1ca9a2 doc: restore targets as pages.
You can't have two mainpage items, and the second was just being
ignored.  This restores them, which makes the left side list longer,
which we may or may not like, but it's at least how it was documented to
be.
2019-06-10 11:10:34 +00:00
Karl Palsson
d0c3678f74 stm32l4: rcc: drop bad function prototype
This was introduced by a bad merge/rebase leaving a dangling header
definition.

Fixes: b8424263 stm32:l4: rcc: Add RTC clock functions
2019-06-02 22:27:15 +00:00
Bruno Randolf
b8424263e8 stm32:l4: rcc: Add RTC clock functions 2019-06-02 22:18:05 +00:00
Bruno Randolf
2c1823f7bb stm32:l4: pwr: Add en/disable_backup_domain_write_protect() 2019-06-02 22:18:05 +00:00
Bruno Randolf
a1f58ea8ae stm32:l4: Add interrupts for STM32L4x5/STM32L4x6
Add all interrups from RM0351
2019-06-02 22:18:05 +00:00
Bruno Randolf
fe722d4643 stm32:l4: rcc: Add helper functions
Add functions for PLL output and 48MHz clock source selection
2019-06-02 22:18:05 +00:00
Bruno Randolf
a1ffdc59f0 stm32:l4: flash: Program in double words
According to RM0351 and RM0394 flash needs to be programmed by double words.
Also fix flash_program() which was wrong anyways.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2019-06-02 22:17:55 +00:00
Karl Palsson
1af3acdba4 stm32: doc: exti: fix missing/wrong groups and move to peripheral_api
Almost all families were missing all docs for the exti apis.
2019-05-21 23:16:59 +00:00
Karl Palsson
b24d7f96b5 stm32: standardize OSPEED values
Make the names match the reference manuals properly, and add missing
names.  Still a long way to go to unify across all families, but this is
at least closer.
2019-05-21 00:05:22 +00:00
Marek Koza
e50ce6a876 stm32l4: Correct memorymap and add the existing CAN library 2019-04-30 20:47:14 +02:00
Guillaume Revaillot
553c876fa5 stm32: exti: define AFIO/SYSCFG_EXTICR_FIELDSIZE for all chip.
While on all current chips, exticr gpio port mux selection is coded on 4 bits,
stm32g0 EXTI_EXTICR register uses 8 bits.  Align all exti header to reference
that value (was previously defined for f0 as SYCFG_EXTICR_SKIP)
2019-01-31 09:57:43 +00:00
Guillaume Revaillot
ff9664389b stm32: exti: move register definition of all current stm32 devices to common_v1
Preparation for stm32g0 support, as this chip's exti register map evolved and is
no longer common ...
2019-01-18 18:33:55 +01:00
Karl Palsson
ad10e96811 stm32l4:dma: add Channel Selection defines
Far from complete support for the channel selection systems on f0/l4,
but at least brings in the defines needed for doing this yourself.

Fixes https://github.com/libopencm3/libopencm3/issues/1001
2018-12-30 21:03:40 +00:00
Karl Palsson
0e58ee2f65 stm32: support i2c3 properly
I2C3 is on many parts, but wasn't properly supported with the register
definitions.  Declare them centrally, just depending on the memorymap
defining them. On some parts, the rcc bits were defined, but not the
base registers.

Fixes: https://github.com/libopencm3/libopencm3/issues/820
2018-08-17 00:15:01 +00:00
Karl Palsson
ddc7ab8c6c stm32l4: flash: don't use misleading names
flash_clear_pgperr_flag is a name used on f247, which is actually most
analogous to the SIZERR bit on l4, (it's a parallelism error)

the bit being cleared originally in this function, PROGERR is a new bit,
and should have it's own name.

Add a function to handle the previously unhandled size/parallelism flag,
and rename the existing one to properly reflect it's new name.
2018-07-29 20:31:17 +00:00
Karl Palsson
eafc46ff24 stm32: flash: extract wait_for_last_operation to top level
This then eliminates the misguided attempts at merging f2/4 and f3 flash
support.  Some headers remain.
2018-07-29 20:31:17 +00:00
Karl Palsson
c272ea410e stm32: flash: move clear all status flags to single common header
We've got a "f" flash file for common apis now, use it.
2018-07-29 20:31:17 +00:00
Karl Palsson
b9448bff16 stm32l4: flash: fix page erase for second bank
l4 is pages, not sectors, so update apis to be consistent. (other
families use page/sector as defined in the reference manual)
Make sure that pages on the second bank can also be erased.  Use the
same style in use for f2/4/7 for sector numbers across banks.
2018-07-29 20:31:17 +00:00
Karl Palsson
850931dbcd stm32: flash_unlock_option_bytes is common code.
The keys differ between some familes, but the documentation and
implementation are standard.
2018-07-29 20:31:17 +00:00
Karl Palsson
7a27795d8c stm32: flash: pull out i/d cache support.
Copied a few times.
2018-07-29 20:31:17 +00:00
Karl Palsson
4840b6bc7e stm32: flash: pull up clear_eop
All the "f" type flash parts have an EOP flag, even if it's in different
bit positions.  Add a header for this common functionality, and move
it's implementation to the existing common file.
2018-07-29 20:31:17 +00:00
Karl Palsson
da7ebafcbe stm32: flash: pull lock/unlock up to common_f.
This is a common operation, so definition in _all, and every part except
l0/l1 have the same implementation.  Bring in an _f file too.
2018-07-29 20:31:17 +00:00
Karl Palsson
b23dccc7ae stm32: flash: pull up prefetch to _all
Turns out, there's lots of common code for flash.  Pull up prefetch
on/off to start with, as there's only a single bit name different.

Pull up the definitions of common API functions too, starting with
flash_set_ws.  Even if the implementations are different, things that
meant to be the same, should be defined centrally.
2018-07-29 20:31:17 +00:00
Karl Palsson
9dd901ba27 stm32: flash: BSY bit has never been writable.
This has been copied around for years, but has never been a writable bit
on any target.
2018-07-29 20:31:17 +00:00
Karl Palsson
b47b967440 doc: use common naming for peripheral apis
Only applied to STM32 doc trees at present.

Instead of declaring a group for "STM32blah" in the doc-blah.h files,
and then trying to put all the common+specific peripheral code into
those groups, (which is what led to the stub doxygen holder empty .c
files)  Just use a standard name like "Peripheral APIS" and place
everything into that.

Demonstrated by converting ADC and USART peripherals, which is
definitely not complete, but it shows how to make things less magical,
and less prone to copy/paste errors.  Now, you can copy/paste and it
will do the right thing, because everyone uses the same group names.

This is also how to unify the mix of "STM32blah->Periphblah" and _also_
the dangling "periph_file" modules in doxygen, it merges them together
properly, as they're intended to be really.
2018-07-03 22:23:00 +00:00
Guillaume Revaillot
bf125e91f9 stm32: rework spi, based on PR #740 and #742.
split spi stuff in three part:
 - v1 : basic spi peripheral
 - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
 - v2 : spi with variable datasize, fifo and other fancy stuff.

v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4

This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
2018-04-28 21:12:27 +00:00
Guillaume Revaillot
207eb07d4c stm32: centralize additionnal iwdg window register definition into iwdg-v2.
stm32f0, l3, l4 are currently sharing the same duplicated header, and
stm32l0 uses the same peripheral. Stop copy-pasting stuff and centralize
definitions into a iwdg_common_v2.h header.
2018-03-28 13:06:57 +00:00
Guillaume Revaillot
b79de32e9e stm32: iwdg: fix typo in (unused) register name 2018-03-27 18:35:23 +02:00
Karl Palsson
1379ab4777 stm32l4: enable common exti functionality
tested on l476 disco board.
2018-03-04 00:02:44 +00:00
Christian Tacke
a1264f5065 stm32l4: usart: Fix USART3 definition/typo
USART*3* should point to *3* not *2*.
2018-02-26 12:53:42 +00:00
Bruno Randolf
ec748dc895 stm32:l4: Add SYSCFG definitions
From RM0394 and RM0351
2018-02-13 23:57:43 +00:00
Bruno Randolf
b438edf45d stm32:l4: Add SPI
Same as F3, tested
2018-02-13 23:57:43 +00:00
Bruno Randolf
075ef82a4b stm32:l4: Enable USB FS support
Reviewed against RM0394 and tested with STM32L433CC.
Aparently some other L4 have USB OTG.
2018-02-13 23:57:42 +00:00
Bruno Randolf
de39ab1584 stm32:l4: Add CRS
Reviewed against RM0394, untested
2018-02-13 23:57:42 +00:00
Bruno Randolf
2dd4655aed stm32:l4: rcc: Add CLK48SEL HSI48
This is not NONE on the L4 but HSI48.

Reviewed against RM0394 and RM0351.
2018-02-13 23:57:42 +00:00
Bruno Randolf
f2c629c4ff stm32:l4: rcc: Add support for HSI48 clock 2018-02-13 23:57:42 +00:00
Bruno Randolf
0cd92c31d6 stm32:l4: Add RTC
Use common, some additional registers missing
2018-02-13 23:57:42 +00:00
Bruno Randolf
c90c9fe801 stm32:l4: Add IWDG
Same as F3, reviewed against RM0394, tested
2018-02-13 23:57:42 +00:00
Karl Palsson
55ea31fd04 stm32l4: crc-v2: enable common code
Possible now that the v2 unification code has landed.
2018-02-13 23:57:42 +00:00
Bruno Randolf
7b6710a914 stm32:l4: Add DMA
Same as L1 according to L1-L4 migration guide, untested
2018-02-13 23:57:42 +00:00
Karl Palsson
368a33773f stm32:l4: usart: add missing header
Fixes: f6796604 stm32:l4: enable usart peripheral
2017-11-10 18:02:14 +00:00
Karl Palsson
181ca054d7 stm32l4: add missing flash wait states
Fixes https://github.com/libopencm3/libopencm3/issues/832
2017-10-02 21:59:58 +00:00
Karl Palsson
29c712326f stm32: rcc: extract osc_bypass functions
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time!  There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
2017-06-08 23:01:45 +00:00
Karl Palsson
d1d511c6f4 stm32: rcc: add reset reason group flags.
Originally suggested in https://github.com/libopencm3/libopencm3/pull/399

At least provide macros for each family that allows easy masking of the
full set of reset reason flags.  Trying to provide a function that
provides these in random upper bits seems unclear at best.
2017-03-30 21:48:08 +00:00