Clearing a single bit in DMA_CCR, then immediately writing a 0 over the entire register is completely redundant on the F1, F3 and L1 DMA peripherals. (Unlike the F2 & F4 DMA Peripheral, where this is required)
This sets the stage for adding DMA to STM32F3xx (when added) and STM32L1xx as the controller appears to be identical in these.