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49 Commits

Author SHA1 Message Date
Björn Mellström
711a87f7ba Fix some warnings when compiling with -Wshadow 
There are still a few more places that would need to be corrected
before -Wshadow could be added by default.
 2021-06-03 12:55:28 +02:00
fabalthazar
c85c946ce3 PRIx32 fix 2021-04-17 14:44:30 +02:00
Uwe Bonnes
653d486ee2 cortexm: Store CPUID in target structure. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
91d1ef8bf6 target/stm32: Use t->idcode with probe. 2020-10-07 20:12:35 +02:00
Uwe Bonnes
9bb2807706 adiv5/romtable: Prepare CortexM devices to read the ROMTABLE 
It seems, writing to DHCSR fails silent when the device is sleeping.
Reading DHCS during sleep may return nonsense.
Repeated write may at some point catch the device running and succeed.
With devices sleeping for long time and running on faster clock the
chance for a successful hotplug gets smaller.

- Try hard to halt a sleeping device
- Prepare vector catch and enable all debug units by TRACENA
- Release reset
- Apply device specific fixes
-- STM32F7: Store old value of DBGMCU_CR, enable debug in sleep in
   DBGMCU before reading PIDR and restore DBGMCU on detach.

Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
 2020-10-07 20:11:17 +02:00
Uwe Bonnes
dc3fd2eb06 Classify debug messages 
Firmware BMP with ENABLE_DEBUG=1 will print WARN and INFO as before.
PC-Hosted BMPwill alway print to stderr. Warn is printed unconditional,
INFO, GDB, TARGET, DONGLE and WIRE will print if their appropriate bit in
cl_debuglevel is set via the -v verbose command line argument.
INFO will go to stdout with -t or -l.
 2020-06-05 14:59:30 +02:00
Uwe Bonnes
9b939f4a3a stm32f4: Fix option byte handling (#654) 
Option bytes are not accessible with level 1 protection, so
Use FLASH_OPTCR(x)
Fix crash with "mon opt write xxxx"
Handle option manipulation better when HW Watchdog fuse is set
Allow abbreviated "mon option x<yyy>" commands
 2020-05-05 12:52:32 +02:00
Uwe Bonnes
ada17ada23 stm32f4/7: Always use largest flashsize for device family (#633, #635, #644) 
Do not care for the FLASHSIZE register. Leave it up to the user to abuse
flash area the ST did not announce.
 2020-04-21 17:04:07 +02:00
Uwe Bonnes
a0e42e229b Make more things static. 
No functional change intendend.
 2020-03-26 18:44:19 +01:00
Uwe Bonnes
bdd76de517 Erase: Fix endless erase when erase-area did not end on (page|block) boarder. 2019-12-08 16:43:19 +01:00
Uwe Bonnes
1cf0b8ac13 Make all arguments for all commands (struct *t, int argc, const char **argv). 
-Wall on gcc8 otherwise warns without -Wno-cast-function-type but older
GCCs/CLang choke on that argument:
error: unknown warning option '-Wno-cast-function-type'; did you mean
 '-Wno-bad-function-cast'? [-Werror,-Wunknown-warning-option]

This adds 24 byte to the binary, as some functions are now called with
additional dummy arguments:
"Pushing and popping garbage to keep the system happy"
 2019-09-29 12:44:55 +02:00
Richard Meadows
600bc9f029 Generate DEBUG warnings and return if malloc/calloc fail. 
This is will make debugging earier if this does happen, rather than
dereferencing the null pointer (or passing it to memcpy, or worse).

blackmagic PR #475
 2019-05-26 18:56:12 +02:00
Uwe Bonnes
56fb0f7766 Handle STM32F730 and STM32H750. 
Flash sector calculation was wrong with small flash sizes.
 2019-02-21 19:19:10 +01:00
Uwe Bonnes
7cc02867ae stm32f4: Fix problems with small flash sizes creating overflow or empty regions. 
Thanks to "DerMeisteRR" for pointing out.
 2019-01-09 12:23:49 +01:00
Uwe Bonnes
9ce05ae67b stm32h7/f7: Store DBGMCU_CR on attach() and restore on detach(). 
On STM32[FH]7, DBG_SLEEP must be set for debugging.
 2019-01-07 13:22:01 +13:00
Uwe Bonnes
6633f74d95 stm32h7/f7: Write DBGMCU_CR only on attach. 
Split probe/attach for STM32H7.
 2019-01-07 13:22:01 +13:00
Uwe Bonnes
8575d3e7a6 stm32f7/h7: Use the DPv2 provided idcode for MCU identification. 2019-01-07 13:22:01 +13:00
Uwe Bonnes
5918608156 STM32F7: Debug does not work with WFI without DBG_SLEEP 2018-07-27 10:59:54 +02:00
Gareth McMullin
c5713ea8d3
Merge pull request #366 from UweBonnes/f7_fix 
stm32f4.c: F76x also has large sector by default.
 2018-07-07 13:03:14 +12:00
Uwe Bonnes
50514ccc31 stm32f4.c: F76x also has large sector by default. 2018-07-05 13:29:43 +02:00
Emil Fresk
5e8c8cae10 Removed debug bits for F4/F7 target, same as all other MCUs now 2018-06-28 16:31:34 +02:00
Uwe Bonnes
f1752c7a1a stm32f4: Allow DWORD parallelism. 
Needs external VPP!
 2018-06-16 13:30:53 +02:00
Uwe Bonnes
15312eb86c stm32f4: Honor parallelism also for erase. 2018-06-16 13:30:53 +02:00
Uwe Bonnes
bfeb6f0db9 stm32f4: Use buffered direct flash write with choosen size. 2018-06-16 13:30:53 +02:00
Piotr Esden-Tempski
077e455a94 Setting the driver string on scan. 
This way swdp_scan and jtag_scan commands will show the chip that was
detected instead of the generic STM32F4 string. The generic name is
most confusing when attaching to an STM32F7 target.
 2018-06-01 12:46:14 -07:00
Gareth McMullin
48d232807e
Merge pull request #337 from adamgreig/stm32f4-ram-size 
Update maximum RAM sizes for F4 and F7 devices
 2018-04-26 13:38:11 +12:00
Adam Greig
e1cefb2031 Update maximum RAM sizes for F4 and F7 devices 2018-04-24 11:06:07 +01:00
Gareth McMullin
63967346cd stm32f4: Don't duplicate resources on reattach. 2018-04-23 10:48:05 +12:00
Gareth McMullin
1fd2a24c2d stm32f4: Only construct memory map at attach. 2018-04-23 10:48:05 +12:00
Gareth McMullin
048e8447a5 target: Only support buffered flash writes 2017-10-13 08:58:37 +13:00
Uwe Bonnes
0aa47113f3 stm32f4: Fix F4 dual bank OPTCR1 to option byte mapping. 2017-10-02 16:22:14 +02:00
Uwe Bonnes
c4d3712b39 stm32f4.c: Rework flash structure recognition. 
Dual bank devices do not have sectors (8)12..15 !
Dual banks devices need to MER1 set for mass erase.
F72x has different FLASHSIZE_BASE
 2017-10-02 16:22:14 +02:00
Gareth McMullin
7663794fdf Merge pull request #247 from schodet/stm32f4-x8-x32 
Allow programming STM32F4 when using a low voltage
 2017-07-09 14:33:06 -07:00
Nicolas Schodet
3846ea4708 stm32f4: allow selection of flash programming parallelism 2017-07-09 23:26:49 +02:00
Gareth McMullin
984f8b3d94 Merge pull request #248 from schodet/typo 
stm32f4: fix typo in target name
 2017-06-22 18:35:29 -07:00
Nicolas Schodet
02ce5e23b6 stm32f4: fix typo in target name 2017-06-19 10:56:20 +02:00
Nicolas Schodet
680aa30d52 stm32f4: add support for STM32F4[67]9 2017-06-19 10:41:38 +02:00
Gordon Smith
1ee1f441d5 stm32f4: write flash using byte access 2017-06-16 14:45:16 +02:00
Uwe Bonnes
408c5a9df2 stm32f4: Try to handle option bytes for more devices. 
Correct the table for the OPTCRx values from errors in documentation and
error when entering the values.
 2017-06-09 13:03:26 +02:00
Uwe Bonnes
8a7455f63e src/target/stm32f4.c: Add STM32F7[2|3]x. 2017-06-09 13:03:26 +02:00
Uwe Bonnes
84e036a804 target/stm32f4: Document FLASH_OPTCR(1|2) registers. 2017-06-09 13:03:26 +02:00
Uwe Bonnes
2216587b39 src/target/stm32f4.c: Remove missleading DTCM comment. 
Use different command string for F74x and F76x.
 2017-06-09 13:03:26 +02:00
Uwe Bonnes
dc1c7611a9 src/target/stm32f4.c: All STM32F7 devs have option bytes at 0x1fff0000. 2017-06-09 13:03:26 +02:00
Uwe Bonnes
e43017d0a6 src/target/stm32f4.c: Add STM32F412 and F413. 
F413 needs its own clause, as there is memory > 1 MB but no second bank.
 2017-06-09 13:03:26 +02:00
Uwe Bonnes
24ed65d6b6 src/target/stm32f4.c: Declare CCMRAM only for devices with CCMRAM. 2017-06-09 13:03:26 +02:00
Gareth McMullin
08c0cafa09 stm32f4: Translate ITCM addresses to AXIM on flash write. 2017-04-18 12:56:33 +12:00
Gareth McMullin
82cb6c8e83 target: Use target_addr for flash routines. 2016-07-13 08:31:09 +12:00
Gareth McMullin
f9bdaf06a4 Move flash stubs to target directory and update readme. 2016-07-13 08:31:09 +12:00
Gareth McMullin
b494279fe5 Move target files into separate directory. 2016-07-13 08:31:09 +12:00