There was no reference to LM4F in in the doc/ subdirectory. Add the needed
infrastructure to generate focumentation for LM4F.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The LM4F provides new registers for system control. Each peripheral
now has its own clock gating control register. The LM4F still supports
the legacy registers for backwards compatibility.
Use SYSCTL_RCGCGPIO instead of SYSCTL_RCGC to enable the GPIO.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add an "#ifdef(LM4F)" clause to include/libopencm3/dispatch/nvic.h
and lib/dispatch/vector_nvic.c. This compiles in the vector table
and allows interrupts to be used.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Specify the -mfloat-abi=hard and -mfpu=fpv4-sp-d16 flags so that FPU
is enabled by default.
While this compiles with FPU support, in order to use the floating point types,
the FPU must be explicitly enabled at runtime.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Fix three distinct issues were present with
examples/lm4f/Makefile.include:
1. Architecture flags were not being passed to the linker. This caused the linker
to link against the wrong libraries when trying to use any C library, causing
hard faults.
2. -lc and -lnosys were not linked against. Try using printf() without -lnosys
3. The makefile erroneously specified -mcpu=cortex-m3 instead of m4.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Create lm4f code infrastructure from the lm3s infrastructure.
As far as the interrupt table is concerned, don't create an irq.yaml. Just
include the LM3S nvic.h. The LM3S vector table seems to be compatible with the
LM4F
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This has only been tested functionally with basic timers, and basic operations.
Advanced timer support has been #ifdefed to compile, but this probably needs more testing.
Despite the L1 being a low power device, my initial focus is on making
it basically compatible with existing devices.
To that end, provide clock setup helper routines that configure it for maximum performance,
allowing some similar clock speeds to F1 devices to help with testing. This requires adding
the power chipset routines to set the voltage range.
Clock setup style is similar to the F4 code, which seems nicer than the overflow of different
routines used on the F1 code.
NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power
code, even though it should be compatible
