0af6d06eda
Extension of code for STM32F1 to allow for dual bank series XL. Small changes to documentation for F2, F4 and L1 to add a parameter reference. Tested with STM32F103RBT6 (note: tests show that the PG bit must be cleared after programming, otherwise a subsequent erase attempt fails. This has been added to flash_program_half_word for F0 and F1 only. A fix for the other families is not included in this PR.)
149 lines
4.9 KiB
C
149 lines
4.9 KiB
C
/** @defgroup flash_defines FLASH Defines
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*
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* @ingroup STM32L1xx_defines
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*
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* @brief Defined Constants and Types for the STM32L1xx FLASH Memory
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2012
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* Karl Palsson <karlp@tweak.net.au>
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*
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* @date 14 January 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming
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* manual.
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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/**@{*/
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- FLASH registers ----------------------------------------------------- */
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#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
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#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
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#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
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#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
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#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
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#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c)
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#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
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#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)
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#define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84)
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/* --- FLASH_ACR values ---------------------------------------------------- */
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#define FLASH_ACR_RUNPD (1 << 4)
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#define FLASH_ACR_SLEEPPD (1 << 3)
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#define FLASH_ACR_ACC64 (1 << 2)
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#define FLASH_ACR_PRFTEN (1 << 1)
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/** @defgroup flash_latency FLASH Wait States
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@ingroup flash_defines
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@{*/
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#define FLASH_ACR_LATENCY_0WS 0x00
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#define FLASH_ACR_LATENCY_1WS 0x01
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/**@}*/
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/* --- FLASH_PECR values. Program/erase control register */
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#define FLASH_PECR_OBL_LAUNCH (1 << 18)
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#define FLASH_PECR_ERRIE (1 << 17)
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#define FLASH_PECR_EOPIE (1 << 16)
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#define FLASH_PECR_PARALLBANK (1 << 15)
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#define FLASH_PECR_FPRG (1 << 10)
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#define FLASH_PECR_ERASE (1 << 9)
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#define FLASH_PECR_FTDW (1 << 8)
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#define FLASH_PECR_FTDW (1 << 8)
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#define FLASH_PECR_DATA (1 << 4)
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#define FLASH_PECR_PROG (1 << 3)
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#define FLASH_PECR_OPTLOCK (1 << 2)
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#define FLASH_PECR_PRGLOCK (1 << 1)
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#define FLASH_PECR_PELOCK (1 << 0)
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/* Power down key register (FLASH_PDKEYR) */
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#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637)
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#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD)
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/* Program/erase key register (FLASH_PEKEYR) */
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#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF)
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#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405)
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/* Program memory key register (FLASH_PRGKEYR) */
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#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF)
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#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516)
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/* Option byte key register (FLASH_OPTKEYR) */
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#define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8)
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#define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627)
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/* --- FLASH_SR values ----------------------------------------------------- */
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#define FLASH_SR_OPTVERRUSR (1 << 12)
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#define FLASH_SR_OPTVERR (1 << 11)
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#define FLASH_SR_SIZEERR (1 << 10)
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#define FLASH_SR_PGAERR (1 << 9)
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#define FLASH_SR_WRPERR (1 << 8)
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#define FLASH_SR_READY (1 << 3)
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#define FLASH_SR_ENDHV (1 << 2)
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#define FLASH_SR_EOP (1 << 1)
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#define FLASH_SR_BSY (1 << 0)
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/* --- FLASH_OBR values ----------------------------------------------------- */
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#define FLASH_OBR_BFB2 (1 << 23)
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#define FLASH_OBR_NRST_STDBY (1 << 22)
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#define FLASH_OBR_NRST_STOP (1 << 21)
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#define FLASH_OBR_IWDG_SW (1 << 20)
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#define FLASH_OBR_BOR_OFF (0x0 << 16)
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#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16)
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#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16)
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#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16)
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#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16)
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#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16)
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#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa)
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#define FLASH_OBR_RDPRT_LEVEL_1 (0x00)
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#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void flash_64bit_enable(void);
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void flash_64bit_disable(void);
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void flash_prefetch_enable(void);
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void flash_prefetch_disable(void);
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void flash_set_ws(uint32_t ws);
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END_DECLS
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/**@}*/
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#endif
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