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Deduplication of flash code for STM32F0 and F1.

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Extension of code for STM32F1 to allow for dual bank series XL.
Small changes to documentation for F2, F4 and L1 to add a parameter reference.

Tested with STM32F103RBT6
(note: tests show that the PG bit must be cleared after programming, otherwise
a subsequent erase attempt fails. This has been added to flash_program_half_word
for F0 and F1 only. A fix for the other families is not included in this PR.)
This commit is contained in:
Ken Sarkies 2014-01-24 16:16:53 +10:30 committed by Frantisek Burian
parent a4d9a41093
commit 0af6d06eda
15 changed files with 565 additions and 370 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
doc/stm32f2/Doxyfile
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@ -26,6 +26,7 @@ EXCLUDE =
EXCLUDE_PATTERNS = *_common_f13.h *_common_f13.c \
*_common_*f013.h *_common_*f013.c \
*_common_*f01.h *_common_*f01.c \
*_common_*f03.h *_common_*f03.c
LAYOUT_FILE = DoxygenLayout_stm32f2.xml

1
doc/stm32f3/Doxyfile
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@ -23,6 +23,7 @@ EXCLUDE = ../../include/libopencm3/stm32/f3/usb.h \
../../include/libopencm3/stm32/f3/usb_desc.h
EXCLUDE_PATTERNS = *_common_*f*24.h *_common_*f*24.c \
*_common_*f01.h *_common_*f01.c \
*_common_bcd.h *_common_bcd.c
LAYOUT_FILE = DoxygenLayout_stm32f3.xml

1
doc/stm32f4/Doxyfile
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@ -26,6 +26,7 @@ EXCLUDE =
EXCLUDE_PATTERNS = *_common_f*3.h *_common_f*3.c \
*_common_*f013.h *_common_*f013.c \
*_common_*f01.h *_common_*f01.c \ \
*_common_*f03.h *_common_*f03.c
LAYOUT_FILE = DoxygenLayout_stm32f4.xml

131
include/libopencm3/stm32/common/flash_common_f01.h Normal file
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@ -0,0 +1,131 @@
/** @addtogroup flash_defines
*
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
*/
/** @cond */
#ifdef LIBOPENCM3_FLASH_H
/** @endcond */
#ifndef LIBOPENCM3_FLASH_COMMON_F01_H
#define LIBOPENCM3_FLASH_COMMON_F01_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- FLASH registers ----------------------------------------------------- */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
/* Only present in STM32F10x XL series */
#define FLASH_KEYR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44)
#define FLASH_SR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C)
#define FLASH_CR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50)
#define FLASH_AR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x54)
/* --- FLASH_OPTION bytes ------------------------------------------------- */
#define FLASH_OPTION_BYTE(i) MMIO16(INFO_BASE+0x0800 + (i)*2)
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_LATENCY_SHIFT 0
#define FLASH_ACR_LATENCY 7
#define FLASH_ACR_PRFTBS (1 << 5)
#define FLASH_ACR_PRFTBE (1 << 4)
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_SR_EOP (1 << 5)
#define FLASH_SR_WRPRTERR (1 << 4)
#define FLASH_SR_PGERR (1 << 2)
#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_EOPIE (1 << 12)
#define FLASH_CR_ERRIE (1 << 10)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_CR_OPTER (1 << 5)
#define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
#define FLASH_OBR_RDPRT_SHIFT 1
#define FLASH_OBR_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void flash_set_ws(uint32_t ws);
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgerr_flag(void);
void flash_clear_eop_flag(void);
void flash_clear_wrprterr_flag(void);
void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
uint32_t flash_get_status_flags(void);
void flash_wait_for_last_operation(void);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_erase_page(uint32_t page_address);
void flash_erase_all_pages(void);
void flash_unlock_option_bytes(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(uint32_t address, uint16_t data);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "flash_common_f01.h should not be included directly,"
#warning "only via flash.h"
#endif
/** @endcond */

65
include/libopencm3/stm32/f0/flash.h
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@ -37,25 +37,20 @@
/**@{*/
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/flash_common_f01.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/* --- FLASH_OPTION values ------------------------------------------------- */
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
/** @defgroup flash_options Option Byte Addresses
@ingroup flash_defines
@{*/
#define FLASH_OPTION_BYTE_0 FLASH_OPTION_BYTE(0)
#define FLASH_OPTION_BYTE_1 FLASH_OPTION_BYTE(1)
#define FLASH_OPTION_BYTE_2 FLASH_OPTION_BYTE(2)
#define FLASH_OPTION_BYTE_3 FLASH_OPTION_BYTE(3)
#define FLASH_OPTION_BYTE_4 FLASH_OPTION_BYTE(4)
#define FLASH_OPTION_BYTE_5 FLASH_OPTION_BYTE(5)
/**@}*/
/*****************************************************************************/
/* Register values */
@ -63,15 +58,14 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_PRFTBS (1 << 5)
#define FLASH_ACR_PRFTBE (1 << 4)
#define FLASH_ACR_LATENCY_SHIFT 0
#define FLASH_ACR_LATENCY 7
/** @defgroup flash_latency FLASH Wait States
@ingroup flash_defines
@{*/
#define FLASH_ACR_LATENCY_000_024MHZ 0
#define FLASH_ACR_LATENCY_024_048MHZ 1
#define FLASH_ACR_LATENCY_0WS 0
#define FLASH_ACR_LATENCY_1WS 1
/**@}*/
/* --- FLASH_SR values ----------------------------------------------------- */
@ -83,16 +77,6 @@
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_OBL_LAUNCH (1 << 13)
#define FLASH_CR_EOPIE (1 << 12)
#define FLASH_CR_ERRIE (1 << 10)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_CR_OPTER (1 << 5)
#define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
@ -107,23 +91,19 @@
#define FLASH_OBR_NRST_STDBY (1 << 10)
#define FLASH_OBR_NRST_STOP (1 << 9)
#define FLASH_OBR_WDG_SW (1 << 8)
#define FLASH_OBR_RDPRT_SHIFT 1
#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_RDPRT_L2 (2 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_OPTERR (1 << 0)
#define FLASH_OBR_RDPRT_L2 (3 << FLASH_OBR_RDPRT_SHIFT)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/* Read protection option byte protection level setting */
#define FLASH_RDP_L0 ((uint8_t)0xaa)
#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */
#define FLASH_RDP_L2 ((uint8_t)0xcc)
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/*****************************************************************************/
/* API Functions */
@ -131,15 +111,6 @@
BEGIN_DECLS
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_set_ws(uint32_t ws);
void flash_wait_busy(void);
void flash_program_u32(uint32_t address, uint32_t data);
void flash_program_u16(uint32_t address, uint16_t data);
void flash_erase_page(uint32_t page_address);
void flash_erase_all_pages(void);
END_DECLS
/**@}*/

82
include/libopencm3/stm32/f1/flash.h
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@ -44,27 +44,37 @@
/**@{*/
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/flash_common_f01.h>
/* --- FLASH registers ----------------------------------------------------- */
/* --- FLASH_OPTION bytes ------------------------------------------------- */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
/** @defgroup flash_options Option Byte Addresses
@ingroup flash_defines
@{*/
#define FLASH_OPTION_BYTE_0 FLASH_OPTION_BYTE(0)
#define FLASH_OPTION_BYTE_1 FLASH_OPTION_BYTE(1)
#define FLASH_OPTION_BYTE_2 FLASH_OPTION_BYTE(2)
#define FLASH_OPTION_BYTE_3 FLASH_OPTION_BYTE(3)
#define FLASH_OPTION_BYTE_4 FLASH_OPTION_BYTE(4)
#define FLASH_OPTION_BYTE_5 FLASH_OPTION_BYTE(5)
#define FLASH_OPTION_BYTE_6 FLASH_OPTION_BYTE(6)
#define FLASH_OPTION_BYTE_7 FLASH_OPTION_BYTE(7)
/**@}*/
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_PRFTBS (1 << 5)
#define FLASH_ACR_PRFTBE (1 << 4)
#define FLASH_ACR_HLFCYA (1 << 3)
/** @defgroup flash_latency FLASH Wait States
@ingroup flash_defines
@{*/
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
/**@}*/
#define FLASH_ACR_HLFCYA (1 << 3)
/* --- FLASH_SR values ----------------------------------------------------- */
@ -75,17 +85,6 @@
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_EOPIE (1 << 12)
#define FLASH_CR_ERRIE (1 << 10)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_CR_OPTER (1 << 5)
#define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
@ -93,40 +92,27 @@
#define FLASH_OBR_NRST_STDBY (1 << 4)
#define FLASH_OBR_NRST_STOP (1 << 3)
#define FLASH_OBR_WDG_SW (1 << 2)
#define FLASH_OBR_RDPRT (1 << 1)
#define FLASH_OBR_OPTERR (1 << 0)
#define FLASH_OBR_RDPRT_EN (1 << FLASH_OBR_RDPRT_SHIFT)
/* --- FLASH Keys -----------------------------------------------------------*/
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/* Read protection option byte protection enable key */
#define FLASH_RDP_KEY ((uint16_t)0x00a5)
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_halfcycle_enable(void);
void flash_halfcycle_disable(void);
void flash_set_ws(uint32_t ws);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgerr_flag(void);
void flash_clear_eop_flag(void);
void flash_clear_wrprterr_flag(void);
void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
uint32_t flash_get_status_flags(void);
void flash_unlock_option_bytes(void);
void flash_erase_all_pages(void);
void flash_erase_page(uint32_t page_address);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_wait_for_last_operation(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(uint32_t address, uint16_t data);
void flash_unlock_upper(void);
void flash_lock_upper(void);
void flash_clear_pgerr_flag_upper(void);
void flash_clear_eop_flag_upper(void);
void flash_clear_wrprterr_flag_upper(void);
void flash_clear_bsy_flag_upper(void);
END_DECLS

4
include/libopencm3/stm32/l1/flash.h
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@ -67,8 +67,12 @@
#define FLASH_ACR_SLEEPPD (1 << 3)
#define FLASH_ACR_ACC64 (1 << 2)
#define FLASH_ACR_PRFTEN (1 << 1)
/** @defgroup flash_latency FLASH Wait States
@ingroup flash_defines
@{*/
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
/**@}*/
/* --- FLASH_PECR values. Program/erase control register */
#define FLASH_PECR_OBL_LAUNCH (1 << 18)

235
lib/stm32/common/flash_common_f01.c Normal file
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@ -0,0 +1,235 @@
/** @addtogroup flash_file
*
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/flash.h>
/*---------------------------------------------------------------------------*/
/** @brief Enable the FLASH Prefetch Buffer
This buffer is used for instruction fetches and is enabled by default after
reset.
Note carefully the clock restrictions under which the prefetch buffer may be
enabled or disabled. Changes are normally made while the clock is running in
the power-on low frequency mode before being set to a higher speed mode.
See the reference manual for details.
*/
void flash_prefetch_buffer_enable(void)
{
FLASH_ACR |= FLASH_ACR_PRFTBE;
}
/*---------------------------------------------------------------------------*/
/** @brief Disable the FLASH Prefetch Buffer
Note carefully the clock restrictions under which the prefetch buffer may be
set to disabled. See the reference manual for details.
*/
void flash_prefetch_buffer_disable(void)
{
FLASH_ACR &= ~FLASH_ACR_PRFTBE;
}
/*---------------------------------------------------------------------------*/
/** @brief Set the Number of Wait States
Used to match the system clock to the FLASH memory access time. See the
reference manual for more information on clock speed ranges for each wait state.
The latency must be changed to the appropriate value <b>before</b> any increase
in clock speed, or <b>after</b> any decrease in clock speed.
@param[in] uint32_t ws: values from @ref flash_latency.
*/
void flash_set_ws(uint32_t ws)
{
FLASH_ACR = (FLASH_ACR & ~FLASH_ACR_LATENCY) | ws;
}
/*---------------------------------------------------------------------------*/
/** @brief Unlock the Flash Program and Erase Controller
This enables write access to the Flash memory. It is locked by default on
reset.
*/
void flash_unlock(void)
{
/* Clear the unlock state. */
FLASH_CR |= FLASH_CR_LOCK;
/* Authorize the FPEC access. */
FLASH_KEYR = FLASH_KEYR_KEY1;
FLASH_KEYR = FLASH_KEYR_KEY2;
}
/*---------------------------------------------------------------------------*/
/** @brief Lock the Flash Program and Erase Controller
Used to prevent spurious writes to FLASH.
*/
void flash_lock(void)
{
FLASH_CR |= FLASH_CR_LOCK;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Programming Error Status Flag
*/
void flash_clear_pgerr_flag(void)
{
FLASH_SR |= FLASH_SR_PGERR;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the End of Operation Status Flag
*/
void flash_clear_eop_flag(void)
{
FLASH_SR |= FLASH_SR_EOP;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Write Protect Error Status Flag
*/
void flash_clear_wrprterr_flag(void)
{
FLASH_SR |= FLASH_SR_WRPRTERR;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Busy Status Flag
*/
void flash_clear_bsy_flag(void)
{
FLASH_SR &= ~FLASH_SR_BSY;
}
/*---------------------------------------------------------------------------*/
/** @brief Wait until Last Operation has Ended
This loops indefinitely until an operation (write or erase) has completed by
testing the busy flag.
*/
void flash_wait_for_last_operation(void)
{
while ((flash_get_status_flags() & FLASH_SR_BSY) == FLASH_SR_BSY);
}
/*---------------------------------------------------------------------------*/
/** @brief Program a 32 bit Word to FLASH
This performs all operations necessary to program a 32 bit word to FLASH memory.
The program error flag should be checked separately for the event that memory
was not properly erased.
Status bit polling is used to detect end of operation.
@param[in] uint32_t address. Full address of flash word to be programmed.
@param[in] uint32_t data.
*/
void flash_program_word(uint32_t address, uint32_t data)
{
flash_program_half_word(address,(uint16_t)data);
flash_program_half_word(address+2,(uint16_t)(data>>16));
}
/*---------------------------------------------------------------------------*/
/** @brief Unlock the Option Byte Access
This enables write access to the option bytes. It is locked by default on
reset.
*/
void flash_unlock_option_bytes(void)
{
/* F1 uses same keys for flash and option */
FLASH_OPTKEYR = FLASH_KEYR_KEY1;
FLASH_OPTKEYR = FLASH_KEYR_KEY2;
}
/*---------------------------------------------------------------------------*/
/** @brief Erase All Option Bytes
This performs all operations necessary to erase the option bytes. These must
first be fully erased before attempting to program them, therefore it is
recommended to check these after an erase attempt.
*/
void flash_erase_option_bytes(void)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) {
flash_unlock_option_bytes();
}
FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
/*---------------------------------------------------------------------------*/
/** @brief Program the Option Bytes
This performs all operations necessary to program the option bytes.
The write protect error flag should be checked separately for the event that
an option byte had not been properly erased before calling this function.
Only the lower 8 bits of the data is significant.
@param[in] uint32_t address. Address of option byte from @ref flash_options.
@param[in] uint16_t data.
*/
void flash_program_option_bytes(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) {
flash_unlock_option_bytes();
}
FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
MMIO16(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}
/**@}*/

3
lib/stm32/common/flash_common_f234.c
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@ -21,7 +21,6 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/**@{*/
@ -35,7 +34,7 @@ programming manual for more information on clock speed ranges. The latency must
be changed to the appropriate value <b>before</b> any increase in clock
speed, or <b>after</b> any decrease in clock speed.
@param[in] uint32_t ws: values 0-7 only.
@param[in] uint32_t ws: values from @ref flash_latency.
*/
void flash_set_ws(uint32_t ws)

4
lib/stm32/common/flash_common_f24.c
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@ -21,7 +21,6 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/**@{*/
@ -396,8 +395,7 @@ void flash_erase_all_sectors(uint32_t program_size)
/** @brief Program the Option Bytes
This performs all operations necessary to program the option bytes.
The write protect error flag should be checked separately for the event that
an option byte was not properly erased.
The option bytes do not need to be erased first.
@param[in] uint32_t data to be programmed.
*/

2
lib/stm32/f0/Makefile
View File

@ -39,7 +39,7 @@ OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o crc.o \
OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \
pwr_common_all.o iwdg_common_all.o rtc_common_l1f024.o \
dma_common_l1f013.o exti_common_all.o spi_common_all.o \
spi_common_f03.o
spi_common_f03.o flash_common_f01.o
VPATH += ../../usb:../:../../cm3:../common

119
lib/stm32/f0/flash.c
View File

@ -14,6 +14,16 @@
* For the STM32F05x, accessing FLASH memory is described in
* section 3 of the STM32F05x Reference Manual.
*
* FLASH memory may be used for data storage as well as code, and may be
* programmatically modified. Note that for firmware upload the STM32F1xx
* provides a built-in bootloader in system memory that can be entered from a
* running program.
*
* FLASH must first be unlocked before programming. In this module a write to
* FLASH is a blocking operation until the end-of-operation flag is asserted.
*
* @note: don't forget to lock it again when all operations are complete.
*
* LGPL License Terms @ref lgpl_license
*/
@ -41,87 +51,35 @@
#include <libopencm3/stm32/flash.h>
/*---------------------------------------------------------------------------*/
/** @brief Enable the FLASH Prefetch Buffer
/** @brief Clear All Status Flags
This buffer is used for instruction fetches and is enabled by default after
reset.
Note carefully the clock restrictions under which the prefetch buffer may be
enabled or disabled. Changes are normally made while the clock is running in
the power-on low frequency mode before being set to a higher speed mode.
See the reference manual for details.
Program error, end of operation, write protect error, busy.
*/
void flash_prefetch_buffer_enable(void)
void flash_clear_status_flags(void)
{
FLASH_ACR |= FLASH_ACR_PRFTBE;
flash_clear_pgerr_flag();
flash_clear_eop_flag();
flash_clear_wrprterr_flag();
flash_clear_bsy_flag();
}
/*---------------------------------------------------------------------------*/
/** @brief Disable the FLASH Prefetch Buffer
/** @brief Read All Status Flags
Note carefully the clock restrictions under which the prefetch buffer may be
set to disabled. See the reference manual for details.
The programming error, end of operation, write protect error and busy flags
are returned in the order of appearance in the status register.
@returns uint32_t. bit 0: busy, bit 2: programming error, bit 4: write protect
error, bit 5: end of operation.
*/
void flash_prefetch_buffer_disable(void)
uint32_t flash_get_status_flags(void)
{
FLASH_ACR &= ~FLASH_ACR_PRFTBE;
}
/*---------------------------------------------------------------------------*/
/** @brief Set the Number of Wait States
Used to match the system clock to the FLASH memory access time. See the
reference manual for more information on clock speed ranges for each wait state.
The latency must be changed to the appropriate value <b>before</b> any increase
in clock speed, or <b>after</b> any decrease in clock speed.
@param[in] uint32_t ws: values 0 or 1 only.
*/
void flash_set_ws(uint32_t ws)
{
FLASH_ACR = (FLASH_ACR & ~FLASH_ACR_LATENCY) | ws;
}
/*---------------------------------------------------------------------------*/
/** @brief Wait for Busy Flag
This loops indefinitely until the busy flag is clear.
*/
void flash_wait_busy(void)
{
while ((FLASH_SR & FLASH_SR_BSY) != 0);
}
/*---------------------------------------------------------------------------*/
/** @brief Program a 32 bit Word to FLASH
This performs all operations necessary to program a 32 bit word to FLASH memory.
The program error flag should be checked separately for the event that memory
was not properly erased.
@param[in] uint32_t address. Full address of flash word to be programmed.
@param[in] uint32_t data.
*/
void flash_program_u32(uint32_t address, uint32_t data)
{
flash_wait_busy();
FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = (uint16_t)data;
flash_wait_busy();
MMIO16(address + 2) = data >> 16;
flash_wait_busy();
FLASH_CR &= ~FLASH_CR_PG;
return (FLASH_SR & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
}
/*---------------------------------------------------------------------------*/
@ -131,19 +89,21 @@ This performs all operations necessary to program a 16 bit word to FLASH memory.
The program error flag should be checked separately for the event that memory
was not properly erased.
@param[in] uint32_t address Full address of flash half word to be programmed.
Status bit polling is used to detect end of operation.
@param[in] uint32_t address. Full address of flash half word to be programmed.
@param[in] uint16_t data.
*/
void flash_program_u16(uint32_t address, uint16_t data)
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_busy();
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_busy();
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PG;
}
@ -163,13 +123,14 @@ the FLASH programming manual for details.
void flash_erase_page(uint32_t page_address)
{
flash_wait_busy();
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
FLASH_CR |= FLASH_CR_STRT;
flash_wait_busy();
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PER;
}
@ -182,13 +143,15 @@ memory. The information block is unaffected.
void flash_erase_all_pages(void)
{
flash_wait_busy();
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_busy();
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
/**@}*/

3
lib/stm32/f1/Makefile
View File

@ -40,7 +40,8 @@ OBJS += crc_common_all.o dac_common_all.o dma_common_l1f013.o \
gpio_common_all.o i2c_common_all.o iwdg_common_all.o \
pwr_common_all.o spi_common_all.o spi_common_l1f124.o \
timer_common_all.o usart_common_all.o usart_common_f124.o \
rcc_common_all.o exti_common_all.o
rcc_common_all.o exti_common_all.o \
flash_common_f01.o
OBJS += usb.o usb_control.o usb_standard.o usb_f103.o usb_f107.o \
usb_fx07_common.o

282
lib/stm32/f1/flash.c
View File

@ -25,6 +25,16 @@
* provides a built-in bootloader in system memory that can be entered from a
* running program.
*
* FLASH must first be unlocked before programming. In this module a write to
* FLASH is a blocking operation until the end-of-operation flag is asserted.
*
* @note: don't forget to lock it again when all operations are complete.
*
* For the large memory XL series, with two banks of FLASH, the upper bank is
* accessed with a second set of registers. In principle both banks can be
* written simultaneously, or one read while the other is written. This module
* does not support the simultaneous write feature.
*
* LGPL License Terms @ref lgpl_license
*/
/*
@ -50,35 +60,10 @@
/**@{*/
#include <libopencm3/stm32/flash.h>
#include <libopencm3/stm32/memorymap.h>
/*---------------------------------------------------------------------------*/
/** @brief Enable the FLASH Prefetch Buffer
This buffer is used for instruction fetches and is enabled by default after
reset.
Note carefully the clock restrictions under which the prefetch buffer may be
enabled or disabled. Changes are normally made while the clock is running in
the power-on low frequency mode before being set to a higher speed mode.
See the reference manual for details.
*/
void flash_prefetch_buffer_enable(void)
{
FLASH_ACR |= FLASH_ACR_PRFTBE;
}
/*---------------------------------------------------------------------------*/
/** @brief Disable the FLASH Prefetch Buffer
Note carefully the clock restrictions under which the prefetch buffer may be
set to disabled. See the reference manual for details.
*/
void flash_prefetch_buffer_disable(void)
{
FLASH_ACR &= ~FLASH_ACR_PRFTBE;
}
/* Memory Size Register */
#define MEMORY_SIZE_REG MMIO32(DESIG_FLASH_SIZE_BASE)
/*---------------------------------------------------------------------------*/
/** @brief Enable the FLASH Half Cycle Mode
@ -107,99 +92,84 @@ void flash_halfcycle_disable(void)
}
/*---------------------------------------------------------------------------*/
/** @brief Set the Number of Wait States
/** @brief Unlock the Flash Program and Erase Controller, upper Bank
Used to match the system clock to the FLASH memory access time. See the
reference manual for more information on clock speed ranges for each wait state.
The latency must be changed to the appropriate value <b>before</b> any increase
in clock speed, or <b>after</b> any decrease in clock speed.
@param[in] uint32_t ws: values 0, 1 or 2 only.
This enables write access to the upper bank of the Flash memory in XL devices.
It is locked by default on reset.
*/
void flash_set_ws(uint32_t ws)
void flash_unlock_upper(void)
{
uint32_t reg32;
if (MEMORY_SIZE_REG > 512) {
reg32 = FLASH_ACR;
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
reg32 |= ws;
FLASH_ACR = reg32;
/* Clear the unlock state. */
FLASH_CR2 |= FLASH_CR_LOCK;
/* Authorize the FPEC access. */
FLASH_KEYR2 = FLASH_KEYR_KEY1;
FLASH_KEYR2 = FLASH_KEYR_KEY2;
}
}
/*---------------------------------------------------------------------------*/
/** @brief Unlock the Flash Program and Erase Controller
This enables write access to the Flash memory. It is locked by default on
reset.
*/
void flash_unlock(void)
{
/* Clear the unlock state. */
FLASH_CR |= FLASH_CR_LOCK;
/* Authorize the FPEC access. */
FLASH_KEYR = FLASH_KEYR_KEY1;
FLASH_KEYR = FLASH_KEYR_KEY2;
}
/*---------------------------------------------------------------------------*/
/** @brief Lock the Flash Program and Erase Controller
/** @brief Lock the Flash Program and Erase Controller, upper Bank
Used to prevent spurious writes to FLASH.
*/
void flash_lock(void)
void flash_lock_upper(void)
{
FLASH_CR |= FLASH_CR_LOCK;
FLASH_CR2 |= FLASH_CR_LOCK;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Programming Error Status Flag
/** @brief Clear the Programming Error Status Flag, upper Bank
*/
void flash_clear_pgerr_flag(void)
void flash_clear_pgerr_flag_upper(void)
{
FLASH_SR |= FLASH_SR_PGERR;
if (MEMORY_SIZE_REG > 512)
FLASH_SR2 |= FLASH_SR_PGERR;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the End of Operation Status Flag
/** @brief Clear the End of Operation Status Flag, upper Bank
*/
void flash_clear_eop_flag(void)
void flash_clear_eop_flag_upper(void)
{
FLASH_SR |= FLASH_SR_EOP;
if (MEMORY_SIZE_REG > 512)
FLASH_SR2 |= FLASH_SR_EOP;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Write Protect Error Status Flag
/** @brief Clear the Write Protect Error Status Flag, upper Bank
*/
void flash_clear_wrprterr_flag(void)
void flash_clear_wrprterr_flag_upper(void)
{
FLASH_SR |= FLASH_SR_WRPRTERR;
if (MEMORY_SIZE_REG > 512)
FLASH_SR2 |= FLASH_SR_WRPRTERR;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Busy Status Flag
/** @brief Clear the Busy Status Flag, upper Bank
*/
void flash_clear_bsy_flag(void)
void flash_clear_bsy_flag_upper(void)
{
FLASH_SR &= ~FLASH_SR_BSY;
if (MEMORY_SIZE_REG > 512)
FLASH_SR2 &= ~FLASH_SR_BSY;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear All Status Flags
Program error, end of operation, write protect error, busy.
Program error, end of operation, write protect error, busy. Both banks cleared.
*/
void flash_clear_status_flags(void)
@ -208,6 +178,12 @@ void flash_clear_status_flags(void)
flash_clear_eop_flag();
flash_clear_wrprterr_flag();
flash_clear_bsy_flag();
if (MEMORY_SIZE_REG > 512) {
flash_clear_pgerr_flag_upper();
flash_clear_eop_flag_upper();
flash_clear_wrprterr_flag_upper();
flash_clear_bsy_flag_upper();
}
}
/*---------------------------------------------------------------------------*/
@ -216,77 +192,25 @@ void flash_clear_status_flags(void)
The programming error, end of operation, write protect error and busy flags
are returned in the order of appearance in the status register.
Flags for the upper bank, where appropriate, are combined with those for
the lower bank using bitwise OR, without distinction.
@returns uint32_t. bit 0: busy, bit 2: programming error, bit 4: write protect
error, bit 5: end of operation.
*/
uint32_t flash_get_status_flags(void)
{
return FLASH_SR &= (FLASH_SR_PGERR |
uint32_t flags = (FLASH_SR & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY);
}
/*---------------------------------------------------------------------------*/
/** @brief Unlock the Option Byte Access
This enables write access to the option bytes. It is locked by default on
reset.
*/
void flash_unlock_option_bytes(void)
{
/* F1 uses same keys for flash and option */
FLASH_OPTKEYR = FLASH_KEYR_KEY1;
FLASH_OPTKEYR = FLASH_KEYR_KEY2;
}
/*---------------------------------------------------------------------------*/
/** @brief Wait until Last Operation has Ended
This loops indefinitely until an operation (write or erase) has completed by
testing the busy flag.
*/
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
/*---------------------------------------------------------------------------*/
/** @brief Program a 32 bit Word to FLASH
This performs all operations necessary to program a 32 bit word to FLASH memory.
The program error flag should be checked separately for the event that memory
was not properly erased.
@param[in] uint32_t address. Full address of flash word to be programmed.
@param[in] uint32_t data.
*/
void flash_program_word(uint32_t address, uint32_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
/* Enable writes to flash. */
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO16(address) = (uint16_t)data;
/* Wait for the write to complete. */
flash_wait_for_last_operation();
/* Enable writes to flash. */
FLASH_CR |= FLASH_CR_PG;
/* Program the second half of the word. */
MMIO16(address + 2) = data >> 16;
/* Wait for the write to complete. */
flash_wait_for_last_operation();
FLASH_SR_BSY));
if (MEMORY_SIZE_REG > 512)
flags |= (FLASH_SR2 & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
return flags;
}
/*---------------------------------------------------------------------------*/
@ -296,6 +220,8 @@ This performs all operations necessary to program a 16 bit word to FLASH memory.
The program error flag should be checked separately for the event that memory
was not properly erased.
Status bit polling is used to detect end of operation.
@param[in] uint32_t address. Full address of flash half word to be programmed.
@param[in] uint16_t data.
*/
@ -304,11 +230,17 @@ void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PG;
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
FLASH_CR2 |= FLASH_CR_PG;
else FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
FLASH_CR2 &= ~FLASH_CR_PG;
else FLASH_CR &= ~FLASH_CR_PG;
}
/*---------------------------------------------------------------------------*/
@ -321,19 +253,29 @@ first be fully erased before attempting to program it.
Note that the page sizes differ between devices. See the reference manual or
the FLASH programming manual for details.
@param[in] uint32_t page_address. Full address of flash psge to be erased.
@param[in] uint32_t page_address. Full address of flash page to be erased.
*/
void flash_erase_page(uint32_t page_address)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
FLASH_CR |= FLASH_CR_STRT;
if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 |= FLASH_CR_PER;
FLASH_AR2 = page_address;
FLASH_CR2 |= FLASH_CR_STRT;
} else {
FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
FLASH_CR |= FLASH_CR_STRT;
}
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PER;
if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000))
FLASH_CR2 &= ~FLASH_CR_PER;
else
FLASH_CR &= ~FLASH_CR_PER;
}
/*---------------------------------------------------------------------------*/
@ -352,52 +294,14 @@ void flash_erase_all_pages(void)
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
/* Repeat for bank 2 */
FLASH_CR2 |= FLASH_CR_MER;
FLASH_CR2 |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR2 &= ~FLASH_CR_MER;
}
/*---------------------------------------------------------------------------*/
/** @brief Erase All Option Bytes
This performs all operations necessary to erase the option bytes. These must
first be fully erased before attempting to program them.
*/
void flash_erase_option_bytes(void)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) {
flash_unlock_option_bytes();
}
FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
/*---------------------------------------------------------------------------*/
/** @brief Program the Option Bytes
This performs all operations necessary to program the option bytes.
The write protect error flag should be checked separately for the event that
an option byte was not properly erased.
@param[in] uint32_t address. Full address of option byte to program.
@param[in] uint16_t data.
*/
void flash_program_option_bytes(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) {
flash_unlock_option_bytes();
}
FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
MMIO16(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}
/**@}*/

2
lib/stm32/l1/flash.c
View File

@ -108,7 +108,7 @@ latency must be changed to the appropriate value <b>before</b> any increase in
clock speed, or <b>after</b> any decrease in clock speed. A latency setting of
zero only applies if 64-bit mode is not used.
@param[in] uint32_t ws: values 0 or 1 only.
@param[in] uint32_t ws: values from @ref flash_latency.
*/
void flash_set_ws(uint32_t ws)