0af6d06eda
Extension of code for STM32F1 to allow for dual bank series XL. Small changes to documentation for F2, F4 and L1 to add a parameter reference. Tested with STM32F103RBT6 (note: tests show that the PG bit must be cleared after programming, otherwise a subsequent erase attempt fails. This has been added to flash_program_half_word for F0 and F1 only. A fix for the other families is not included in this PR.)
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/** @defgroup flash_file FLASH
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*
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* @ingroup STM32L1xx
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*
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* @brief <b>libopencm3 STM32L1xx FLASH</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2010
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* Thomas Otto <tommi@viadmin.org>
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* @author @htmlonly © @endhtmlonly 2010
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* Mark Butler <mbutler@physics.otago.ac.nz>
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* @author @htmlonly © @endhtmlonly 2012
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* Karl Palsson <karlp@tweak.net.au>
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*
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* @date 14 January 2014
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*
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* For the STM32L1xx, accessing FLASH memory is described briefly in
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* section 2.3.3 of the STM32L1xx Reference Manual.
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* For detailed programming information see:
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* PM0062 programming manual: STM32L1xxxx Flash and EEPROM programming
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* March 2012, Doc ID 16024 Rev 5
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/flash.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Enable 64 Bit Programming Mode
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*/
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void flash_64bit_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_ACC64;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable 32 Bit Programming Mode
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This mode is a low power mode. It must be used at low frequencies and does not
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allow prefetch or wait states to be used.
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*/
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void flash_64bit_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_ACC64;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable the FLASH Prefetch Buffer
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This buffer is used for instruction fetches and is enabled by default after
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reset.
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Note carefully the restrictions under which the prefetch buffer may be
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enabled or disabled. Prefetch is only available when 64-bit
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access is enabled.
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*/
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void flash_prefetch_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_PRFTEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable the FLASH Prefetch Buffer
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Note carefully the restrictions under which the prefetch buffer may be
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set to disabled. See the reference and programming manuals for details.
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*/
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void flash_prefetch_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_PRFTEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the Number of Wait States
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Used to match the system clock to the FLASH memory access time. See the
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programming manual for more information on clock speed and voltage ranges. The
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latency must be changed to the appropriate value <b>before</b> any increase in
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clock speed, or <b>after</b> any decrease in clock speed. A latency setting of
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zero only applies if 64-bit mode is not used.
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@param[in] uint32_t ws: values from @ref flash_latency.
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*/
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void flash_set_ws(uint32_t ws)
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{
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uint32_t reg32;
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reg32 = FLASH_ACR;
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reg32 &= ~(1 << 0);
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reg32 |= ws;
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FLASH_ACR = reg32;
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}
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/**@}*/
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