1755098617
L4 and F3 actually have the same bits to write in the same order, but F3 hides the name of the deep power down bit. Keep the like that for now, but there's a standard API for enabling and disabling the regulator.
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/** @defgroup adc_defines ADC Defines
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*
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* @brief <b>Defined Constants and Types for the STM32L4xx Analog to Digital
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* Converter</b>
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*
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* @ingroup STM32L4xx_defines
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*
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* @version 1.0.0
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*
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* @date 24 Oct 2015
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/stm32/common/adc_common_v2.h>
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#include <libopencm3/stm32/common/adc_common_v2_multi.h>
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/** @defgroup adc_reg_base ADC register base addresses
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC1 ADC1_BASE
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#define ADC2 ADC2_BASE
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#define ADC3 ADC3_BASE
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/**@}*/
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_CHANNEL_VREF 0
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#define ADC_CHANNEL_TEMP 17
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#define ADC_CHANNEL_VBAT 18
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/**@}*/
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/* ADC_CR Values ------------------------------------------------------------*/
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/* DEEPPWD: Deep power down */
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#define ADC_CR_DEEPPWD (1 << 29)
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/* ADVREGEN: Voltage regulator enable bit */
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#define ADC_CR_ADVREGEN (1 << 28)
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/****************************************************************************/
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/* ADC_SMPRx ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample ADC Sample Time Selection values
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@ingroup adc_defines
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@{*/
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#define ADC_SMPR_SMP_2DOT5CYC 0x0
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#define ADC_SMPR_SMP_6DOT5CYC 0x1
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#define ADC_SMPR_SMP_12DOT5CYC 0x2
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#define ADC_SMPR_SMP_24DOT5CYC 0x3
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#define ADC_SMPR_SMP_47DOT5CYC 0x4
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#define ADC_SMPR_SMP_92DOT5CYC 0x5
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#define ADC_SMPR_SMP_247DOT5CYC 0x6
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#define ADC_SMPR_SMP_640DOT5CYC 0x7
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/**@}*/
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BEGIN_DECLS
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END_DECLS
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#endif
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