147 lines
4.3 KiB
C
147 lines
4.3 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @defgroup CM3_nvic_defines NVIC Defines
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@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
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@ingroup CM3_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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@date 18 August 2012
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LGPL License Terms @ref lgpl_license
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*/
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/**@{*/
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#ifndef LIBOPENCM3_NVIC_H
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#define LIBOPENCM3_NVIC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/cm3/memorymap.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \
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(iser_id * 4))
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/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \
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(icer_id * 4))
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/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
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/* ISPR: Interrupt Set Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \
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(ispr_id * 4))
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/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
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/* ICPR: Interrupt Clear Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \
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(icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \
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(iabr_id * 4))
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \
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ipr_id)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M3 and M4 System Interrupts */
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/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
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@ingroup CM3_nvic_defines
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IRQ numbers -3 and -6 to -9 are reserved
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@{*/
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#define NVIC_NMI_IRQ -14
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#define NVIC_HARD_FAULT_IRQ -13
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#define NVIC_MEM_MANAGE_IRQ -12
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#define NVIC_BUS_FAULT_IRQ -11
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#define NVIC_USAGE_FAULT_IRQ -10
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/* irq numbers -6 to -9 are reserved */
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#define NVIC_SV_CALL_IRQ -5
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#define DEBUG_MONITOR_IRQ -4
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/* irq number -3 reserved */
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#define NVIC_PENDSV_IRQ -2
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#define NVIC_SYSTICK_IRQ -1
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/**@}*/
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/* Note: User interrupts are family specific and are defined in a family
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* specific header file in the corresponding subfolder.
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*/
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#define WEAK __attribute__((weak))
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#include <libopencm3/dispatch/nvic.h>
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/* --- NVIC functions ------------------------------------------------------ */
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BEGIN_DECLS
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void nvic_enable_irq(uint8_t irqn);
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void nvic_disable_irq(uint8_t irqn);
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uint8_t nvic_get_pending_irq(uint8_t irqn);
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void nvic_set_pending_irq(uint8_t irqn);
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void nvic_clear_pending_irq(uint8_t irqn);
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uint8_t nvic_get_active_irq(uint8_t irqn);
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uint8_t nvic_get_irq_enabled(uint8_t irqn);
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void nvic_set_priority(uint8_t irqn, uint8_t priority);
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void nvic_generate_software_interrupt(uint16_t irqn);
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void WEAK reset_handler(void);
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void WEAK nmi_handler(void);
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void WEAK hard_fault_handler(void);
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void WEAK mem_manage_handler(void);
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void WEAK bus_fault_handler(void);
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void WEAK usage_fault_handler(void);
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void WEAK sv_call_handler(void);
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void WEAK debug_monitor_handler(void);
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void WEAK pend_sv_handler(void);
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void WEAK sys_tick_handler(void);
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END_DECLS
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/**@}*/
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#endif
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