We are currently using the same code for CM0 CM3 and CM4 cores. This
patch is a bodge that disables sync on the LPC43xx/M0 core, it would be
nicer to probably implement a dispatch system similar to the one used in
stm32 peripheral support so that we can accomodate the different
features of the cortex cores. I (esden) assume we will run into more
incompatibilities in the future between the cortex cores.