439 lines
17 KiB
C
439 lines
17 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_UART_H
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#define LPC43XX_UART_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* UART port base addresses (for convenience) */
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#define UART0 USART0_BASE /* APB0 */
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#define UART1 UART1_BASE /* APB0 */
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#define UART2 USART2_BASE /* APB2 */
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#define UART3 USART3_BASE /* APB2 */
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/* --- UART registers ------------------------------------------------------- */
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/* Receiver Buffer Register (DLAB=0) Read Only */
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#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */
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/* Transmitter Holding Register (DLAB=0) Write Only */
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#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */
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/* Divisor Latch LSB Register (DLAB=1) */
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#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */
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/* Divisor Latch MSB Register (DLAB=1) */
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#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */
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/* Interrupt Enable Register (DLAB=0) */
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#define UART_IER(port) MMIO32(port + 0x004)
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/* Interrupt ID Register Read Only */
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#define UART_IIR(port) MMIO32(port + 0x008)
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/* FIFO Control Register Write Only */
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#define UART_FCR(port) MMIO32(port + 0x008)
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/* Line Control Register */
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#define UART_LCR(port) MMIO32(port + 0x00C)
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/* MCR only for UART1 */
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/* Line Status Register */
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#define UART_LSR(port) MMIO32(port + 0x014)
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/* Auto Baud Control Register */
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#define UART_ACR(port) MMIO32(port + 0x020)
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/* IrDA Control Register only for UART0/2/3 */
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#define UART_ICR(port) MMIO32(port + 0x024)
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/* Fractional Divider Register */
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#define UART_FDR(port) MMIO32(port + 0x028)
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/* Oversampling Register only for UART0/2/3 */
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#define UART_OSR(port) MMIO32(port + 0x02C)
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/* Half-Duplex enable Register only for UART0/2/3 */
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#define UART_HDEN(port) MMIO32(port + 0x040)
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/* Smart card Interface Register Only for UART0/2/3 */
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#define UART_SCICTRL(port) MMIO32(port + 0x048)
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/* RS-485/EIA-485 Control Register */
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#define UART_RS485CTRL(port) MMIO32(port + 0x04C)
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/* RS-485/EIA-485 Address Match Register */
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#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050)
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/* RS-485/EIA-485 Direction Control Delay Register */
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#define UART_RS485DLY(port) MMIO32(port + 0x054)
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/* Synchronous Mode Control Register only for UART0/2/3 */
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#define UART_SYNCCTRL(port) MMIO32(port + 0x058)
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/* Transmit Enable Register */
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#define UART_TER(port) MMIO32(port + 0x05C)
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/* --------------------- BIT DEFINITIONS ----------------------------------- */
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Receiver Buffer Register
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**********************************************************************/
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/* UART Received Buffer mask bit (8 bits) */
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#define UART_RBR_MASKBIT ((uint8_t)0xFF)
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Transmit Holding Register
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**********************************************************************/
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/* UART Transmit Holding mask bit (8 bits) */
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#define UART_THR_MASKBIT ((uint8_t)0xFF)
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Divisor Latch LSB register
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**********************************************************************/
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/* Macro for loading least significant halfs of divisors */
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#define UART_LOAD_DLL(div) ((div) & 0xFF)
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/* Divisor latch LSB bit mask */
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#define UART_DLL_MASKBIT ((uint8_t)0xFF)
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Divisor Latch MSB register
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**********************************************************************/
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/* Divisor latch MSB bit mask */
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#define UART_DLM_MASKBIT ((uint8_t)0xFF)
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/* Macro for loading most significant halfs of divisors */
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#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
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/***********************************************************************
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* Macro defines for Macro defines for UART interrupt enable register
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**********************************************************************/
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/* RBR Interrupt enable*/
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#define UART_IER_RBRINT_EN (1 << 0)
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/* THR Interrupt enable*/
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#define UART_IER_THREINT_EN (1 << 1)
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/* RX line status interrupt enable*/
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#define UART_IER_RLSINT_EN (1 << 2)
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/* Modem status interrupt enable */
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#define UART1_IER_MSINT_EN (1 << 3)
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/* CTS1 signal transition interrupt enable */
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#define UART1_IER_CTSINT_EN (1 << 7)
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/* Enables the end of auto-baud interrupt */
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#define UART_IER_ABEOINT_EN (1 << 8)
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/* Enables the auto-baud time-out interrupt */
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#define UART_IER_ABTOINT_EN (1 << 9)
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/* UART interrupt enable register bit mask */
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#define UART_IER_BITMASK ((uint32_t)(0x307))
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/* UART1 interrupt enable register bit mask */
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#define UART1_IER_BITMASK ((uint32_t)(0x38F))
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/**********************************************************************
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* Macro defines for Macro defines for UART interrupt identification register
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**********************************************************************/
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/* Interrupt Status - Active low */
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#define UART_IIR_INTSTAT_PEND (1 << 0)
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/* Interrupt identification: Modem interrupt*/
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#define UART1_IIR_INTID_MODEM (0 << 1)
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/* Interrupt identification: THRE interrupt*/
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#define UART_IIR_INTID_THRE (1 << 1)
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/* Interrupt identification: Receive data available*/
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#define UART_IIR_INTID_RDA (2 << 1)
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/* Interrupt identification: Receive line status*/
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#define UART_IIR_INTID_RLS (3 << 1)
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/* Interrupt identification: Character time-out indicator*/
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#define UART_IIR_INTID_CTI (6 << 1)
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/* Interrupt identification: Interrupt ID mask */
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#define UART_IIR_INTID_MASK (7 << 1)
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/* These bits are equivalent to UnFCR[0] */
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#define UART_IIR_FIFO_EN (3 << 6)
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/* End of auto-baud interrupt */
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#define UART_IIR_ABEO_INT (1 << 8)
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/* Auto-baud time-out interrupt */
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#define UART_IIR_ABTO_INT (1 << 9)
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/* UART interrupt identification register bit mask */
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#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
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/**********************************************************************
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* Macro defines for Macro defines for UART FIFO control register
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**********************************************************************/
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/* UART FIFO enable */
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#define UART_FCR_FIFO_EN (1 << 0)
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/* UART FIFO RX reset */
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#define UART_FCR_RX_RS (1 << 1)
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/* UART FIFO TX reset */
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#define UART_FCR_TX_RS (1 << 2)
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/* UART DMA mode selection */
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#define UART_FCR_DMAMODE_SEL (1 << 3)
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/* UART FIFO trigger level 0: 1 character */
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#define UART_FCR_TRG_LEV0 (0 << 6)
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/* UART FIFO trigger level 1: 4 character */
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#define UART_FCR_TRG_LEV1 (1 << 6)
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/* UART FIFO trigger level 2: 8 character */
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#define UART_FCR_TRG_LEV2 (2 << 6)
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/* UART FIFO trigger level 3: 14 character */
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#define UART_FCR_TRG_LEV3 (3 << 6)
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/* UART FIFO control bit mask */
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#define UART_FCR_BITMASK ((uint8_t)(0xCF))
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#define UART_TX_FIFO_SIZE (16)
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/**********************************************************************
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* Macro defines for Macro defines for UART line control register
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**********************************************************************/
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/* UART 5 bit data mode */
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#define UART_LCR_WLEN5 (0 << 0)
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/* UART 6 bit data mode */
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#define UART_LCR_WLEN6 (1 << 0)
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/* UART 7 bit data mode */
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#define UART_LCR_WLEN7 (2 << 0)
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/* UART 8 bit data mode */
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#define UART_LCR_WLEN8 (3 << 0)
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/* UART One Stop Bits */
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#define UART_LCR_ONE_STOPBIT (0 << 2)
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/* UART Two Stop Bits */
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#define UART_LCR_TWO_STOPBIT (1 << 2)
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/* UART Parity Disabled / No Parity */
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#define UART_LCR_NO_PARITY (0 << 3)
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/* UART Parity Enable */
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#define UART_LCR_PARITY_EN (1 << 3)
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/* UART Odd Parity Select */
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#define UART_LCR_PARITY_ODD (0 << 4)
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/* UART Even Parity Select */
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#define UART_LCR_PARITY_EVEN (1 << 4)
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/* UART force 1 stick parity */
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#define UART_LCR_PARITY_SP_1 (1 << 5)
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/* UART force 0 stick parity */
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#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4))
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/* UART Transmission Break enable */
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#define UART_LCR_BREAK_EN (1 << 6)
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/* UART Divisor Latches Access bit enable */
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#define UART_LCR_DLAB_EN (1 << 7)
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/* UART line control bit mask */
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#define UART_LCR_BITMASK ((uint8_t)(0xFF))
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/**********************************************************************
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* Macro defines for Macro defines for UART line status register
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**********************************************************************/
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/* Line status register: Receive data ready */
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#define UART_LSR_RDR (1 << 0)
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/* Line status register: Overrun error */
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#define UART_LSR_OE (1 << 1)
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/* Line status register: Parity error */
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#define UART_LSR_PE (1 << 2)
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/* Line status register: Framing error */
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#define UART_LSR_FE (1 << 3)
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/* Line status register: Break interrupt */
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#define UART_LSR_BI (1 << 4)
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/* Line status register: Transmit holding register empty */
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#define UART_LSR_THRE (1 << 5)
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/* Line status register: Transmitter empty */
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#define UART_LSR_TEMT (1 << 6)
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/* Error in RX FIFO */
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#define UART_LSR_RXFE (1 << 7)
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/* UART Line status bit mask */
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#define UART_LSR_BITMASK ((uint8_t)(0xFF))
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#define UART_LSR_ERROR_MASK \
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(UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE)
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/**********************************************************************
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* Macro defines for Macro defines for UART Scratch Pad Register
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**********************************************************************/
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/* UART Scratch Pad bit mask */
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#define UART_SCR_BIMASK ((uint8_t)(0xFF))
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/***********************************************************************
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* Macro defines for Macro defines for UART Auto baudrate control register
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**********************************************************************/
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/* UART Auto-baud start */
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#define UART_ACR_START (1 << 0)
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/* UART Auto baudrate Mode 1 */
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#define UART_ACR_MODE (1 << 1)
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/* UART Auto baudrate restart */
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#define UART_ACR_AUTO_RESTART (1 << 2)
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/* UART End of auto-baud interrupt clear */
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#define UART_ACR_ABEOINT_CLR (1 << 8)
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/* UART Auto-baud time-out interrupt clear */
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#define UART_ACR_ABTOINT_CLR (1 << 9)
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/* UART Auto Baudrate register bit mask */
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#define UART_ACR_BITMASK ((uint32_t)(0x307))
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/*********************************************************************
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* Macro defines for Macro defines for UART IrDA control register
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**********************************************************************/
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/* IrDA mode enable */
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#define UART_ICR_IRDAEN (1 << 0)
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/* IrDA serial input inverted */
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#define UART_ICR_IRDAINV (1 << 1)
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/* IrDA fixed pulse width mode */
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#define UART_ICR_FIXPULSE_EN (1 << 2)
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/* PulseDiv - Configures the pulse when FixPulseEn = 1 */
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#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
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/* UART IRDA bit mask */
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#define UART_ICR_BITMASK ((uint32_t)(0x3F))
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/**********************************************************************
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* Macro defines for Macro defines for UART half duplex register
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**********************************************************************/
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/* enable half-duplex mode*/
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#define UART_HDEN_HDEN (1 << 0)
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/**********************************************************************
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* Macro defines for Macro defines for UART smart card interface control register
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**********************************************************************/
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/* enable asynchronous half-duplex smart card interface*/
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#define UART_SCICTRL_SCIEN (1 << 0)
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/* NACK response is inhibited*/
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#define UART_SCICTRL_NACKDIS (1 << 1)
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/* ISO7816-3 protocol T1 is selected*/
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#define UART_SCICTRL_PROTSEL_T1 (1 << 2)
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/* number of retransmission*/
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#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5))
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/* Extra guard time*/
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#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8))
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/*********************************************************************
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* Macro defines for Macro defines for UART synchronous control register
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**********************************************************************/
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/* enable synchronous mode*/
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#define UART_SYNCCTRL_SYNC (1 << 0)
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/* synchronous master mode*/
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#define UART_SYNCCTRL_CSRC_MASTER (1 << 1)
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/* sample on falling edge*/
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#define UART_SYNCCTRL_FES (1 << 2)
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/* to be defined*/
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#define UART_SYNCCTRL_TSBYPASS (1 << 3)
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/* continuous running clock enable (master mode only) */
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#define UART_SYNCCTRL_CSCEN (1 << 4)
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/* Do not send start/stop bit */
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#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5)
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/* stop continuous clock */
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#define UART_SYNCCTRL_CCCLR (1 << 6)
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/*********************************************************************
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* Macro defines for Macro defines for UART Fractional divider register
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**********************************************************************/
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/* Baud-rate generation pre-scaler divisor */
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#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
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/* Baud-rate pre-scaler multiplier value */
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#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
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/* UART Fractional Divider register bit mask */
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#define UART_FDR_BITMASK ((uint32_t)(0xFF))
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/*********************************************************************
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* Macro defines for Macro defines for UART Tx Enable register
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**********************************************************************/
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#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */
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/**********************************************************************
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* Macro defines for Macro defines for UART FIFO Level register
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**********************************************************************/
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/* Reflects the current level of the UART receiver FIFO */
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#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F))
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/* Reflects the current level of the UART transmitter FIFO */
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#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F))
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/* UART FIFO Level Register bit mask */
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#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))
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/*********************************************************************
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* UART enum
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**********************************************************************/
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/*
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* UART Databit type definitions
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*/
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typedef enum {
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UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */
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UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */
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UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */
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UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */
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} uart_databit_t;
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/*
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* UART Stop bit type definitions
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*/
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typedef enum {
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/* UART 1 Stop Bits Select */
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UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT,
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/* UART 2 Stop Bits Select */
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UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT
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} uart_stopbit_t;
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/*
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* UART Parity type definitions
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*/
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typedef enum {
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/* No parity */
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UART_PARITY_NONE = UART_LCR_NO_PARITY,
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/* Odd parity */
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UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN),
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/* Even parity */
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UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN),
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/* Forced 1 stick parity */
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UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN),
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/* Forced 0 stick parity */
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UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN)
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} uart_parity_t;
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typedef enum {
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UART0_NUM = UART0,
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UART1_NUM = UART1,
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UART2_NUM = UART2,
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UART3_NUM = UART3
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} uart_num_t;
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typedef enum {
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UART_NO_ERROR = 0,
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UART_TIMEOUT_ERROR = 1
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} uart_error_t;
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typedef enum {
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UART_RX_NO_DATA = 0,
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UART_RX_DATA_READY = 1,
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UART_RX_DATA_ERROR = 2
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} uart_rx_data_ready_t;
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/* function prototypes */
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BEGIN_DECLS
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/* Init UART and set PLL1 as clock source (PCLK) */
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void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
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uart_stopbit_t data_nb_stop, uart_parity_t data_parity,
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uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval);
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uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num);
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uint8_t uart_read(uart_num_t uart_num);
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uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
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uart_error_t *error);
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void uart_write(uart_num_t uart_num, uint8_t data);
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END_DECLS
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#endif
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