11 Commits

Author	SHA1	Message	Date
Niels Moseley	363c6c8c62	* Fixed issues for the borken ISE verilog compiler. ... * Added beginnings of Spartan 3E starterkit board project.	2018-01-12 02:29:13 +01:00
Niels Moseley	eab24a0896	Updated license information in each verilog source file.	2018-01-12 02:06:27 +01:00
Niels Moseley	a2432a5e55	Added 2nd order sigma-delta DAC. Added changes suggested by Clifford Wolf.	2017-10-26 16:39:09 +02:00
Niels Moseley	7d1198ee1b	Almost working DE0 board version	2017-10-26 00:47:50 +02:00
Niels Moseley	10d9735e11	First working simulation of 'hello, world' :)	2017-10-24 21:49:05 +02:00
Niels Moseley	31163effd9	Updated filter engine FSM to have named states and separated clocked and non-clocked processes. Fixed bug in spmul which caused incorrect sign handling in final product	2017-10-24 19:40:56 +02:00
Niels Moseley	22b3443358	Fixed python script to generate sign-magnitude coeffs instead of 2s complement ones. Filter engine FSM needs revisiting.	2017-10-24 00:34:54 +02:00
Niels Moseley	704cd3d4cb	non-working top level	2017-10-23 02:15:45 +02:00
Niels Moseley	bdcd8a3d8f	Removed superfluous comments. Added 2x/double_mode for A1 coefficients to filter engine.	2017-10-21 00:38:12 +02:00
Niels Moseley	cf89706963	Fix bugs in the filter engine FSM. Verified correct behaviour with a 2nd order section.	2017-10-18 22:03:16 +02:00
Niels Moseley	541fb228ed	Added filter engine	2017-10-18 17:19:15 +02:00