stm32f3: Some additional f3 clock functions for the i2c.
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@ -433,6 +433,9 @@ void rcc_set_main_pll_hsi(uint32_t pll);
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uint32_t rcc_get_system_clock_source(void);
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void rcc_backupdomain_reset(void);
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void rcc_clock_setup_hsi(const clock_scale_t *clock);
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void rcc_set_i2c_clock_hsi(uint32_t i2c);
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void rcc_set_i2c_clock_sysclk(uint32_t i2c);
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uint32_t rcc_get_i2c_clocks(void);
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END_DECLS
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@ -24,6 +24,7 @@
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/f3/rcc.h>
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#include <libopencm3/stm32/f3/flash.h>
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#include <libopencm3/stm32/f3/i2c.h>
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/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
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uint32_t rcc_ppre1_frequency = 8000000;
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@ -422,3 +423,25 @@ void rcc_backupdomain_reset(void)
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RCC_BDCR &= ~RCC_BDCR_BDRST;
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}
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void rcc_set_i2c_clock_hsi(uint32_t i2c) {
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if (i2c==I2C1) {
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RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW;
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}
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if (i2c==I2C2) {
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RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW;
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}
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}
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void rcc_set_i2c_clock_sysclk(uint32_t i2c) {
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if (i2c==I2C1) {
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RCC_CFGR3 |= RCC_CFGR3_I2C1SW;
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}
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if (i2c==I2C2) {
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RCC_CFGR3 |= RCC_CFGR3_I2C2SW;
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}
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}
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uint32_t rcc_get_i2c_clocks(void)
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{
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return(RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW));
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}
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